Jędrzej Boczar
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6943a1a4a5
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lpddr4: initial PHY logic and simulation tests
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2021-03-25 15:19:08 +01:00 |
Florent Kermarrec
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2d021c842e
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test/reference: update.
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2021-02-16 18:35:53 +01:00 |
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enjoy-digital
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2c60861929
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Merge pull request #232 from antmicro/jboc/init-mr
init: make the write leveling MR bit configurable
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2021-02-02 09:36:46 +01:00 |
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Jędrzej Boczar
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b3ce582891
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test: update ddr3 and ddr4 reference headers to new MR_WLVL defines
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2021-01-29 12:49:19 +01:00 |
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Jędrzej Boczar
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a1e7d805ec
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test: improve error messages when comparing files in test_init.py
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2021-01-28 17:44:13 +01:00 |
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Florent Kermarrec
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c29c898af4
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platforms/targets: switch to LiteX-Boards.
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2021-01-04 14:11:32 +01:00 |
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Florent Kermarrec
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103072c68a
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test/reference: update.
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2020-12-17 18:21:53 +01:00 |
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Florent Kermarrec
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b6252345af
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test/reference: update ddr4.
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2020-11-17 17:12:02 +01:00 |
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Florent Kermarrec
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df73b982ee
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test/reference: update
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2020-10-12 18:50:31 +02:00 |
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Florent Kermarrec
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39178ce460
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test: add minimal OSERDESE2/OSERDESE3 simulations to check Data/Tristate latencies.
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2020-10-02 12:30:19 +02:00 |
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Florent Kermarrec
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f8ee596464
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test/reference: update.
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2020-09-30 19:49:38 +02:00 |
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Florent Kermarrec
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6d063b196c
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test/reference: update.
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2020-09-30 18:06:48 +02:00 |
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Florent Kermarrec
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c4d7083677
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test/reference: update.
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2020-09-30 13:29:39 +02:00 |
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Florent Kermarrec
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7ccb7d8f16
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test/reference: update.
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2020-09-24 15:03:35 +02:00 |
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Florent Kermarrec
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8525a27762
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test/reference: update.
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2020-09-15 20:00:55 +02:00 |
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Florent Kermarrec
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e56f74e08b
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test/reference: update.
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2020-09-07 19:37:03 +02:00 |
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Florent Kermarrec
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ac825e5112
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add SPDX License identifier to header and specify file is part of LiteDRAM.
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2020-08-23 15:52:08 +02:00 |
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Florent Kermarrec
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198bcbab67
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test/reference: update.
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2020-08-07 23:14:09 +02:00 |
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Florent Kermarrec
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16fd46bf35
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frontend: rename adaptation to adapter.
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2020-08-05 11:10:42 +02:00 |
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enjoy-digital
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02e67ec7c5
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Merge pull request #192 from antmicro/jboc/port-adaptation
Implement LiteDRAMNativePortUpConverter with mode="both"
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2020-07-28 19:02:33 +02:00 |
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enjoy-digital
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c4c8803f4f
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Merge pull request #204 from antmicro/jboc/spd-read
Add DDR4 SPD EEPROM data parser
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2020-06-04 08:54:59 +02:00 |
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Jędrzej Boczar
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8fedc3fcd2
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frontend/fifo: increase FIFO level after data has actually been written
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2020-06-03 16:13:28 +02:00 |
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Jędrzej Boczar
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863c45a114
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test/spd_data: add missing files to tracking
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2020-06-02 15:19:53 +02:00 |
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Jędrzej Boczar
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a8f2c044c9
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modules: add DDR4SPDData parser
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2020-06-02 12:16:41 +02:00 |
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enjoy-digital
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d62fd24c81
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Merge pull request #201 from antmicro/jboc/spd-read
modules/spd: save SPD data in SDRAMModule
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2020-06-01 21:16:58 +02:00 |
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Jędrzej Boczar
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4233f86112
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modules/spd: save SPD data in SDRAMModule to allow for runtime verification
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2020-06-01 16:56:41 +02:00 |
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Florent Kermarrec
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639a31fdd2
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test/test_timing: update test_txxd_controller.
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2020-05-20 23:40:01 +02:00 |
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Florent Kermarrec
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fe48a9290c
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test/reference: update.
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2020-05-19 08:16:11 +02:00 |
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Jędrzej Boczar
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22bd01c014
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frontend/wishbone: simplify by reusing LiteDRAMNativePortConverter
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2020-05-13 17:14:42 +02:00 |
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Jędrzej Boczar
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efe9a44c93
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frontend/adaptation: clean up LiteDRAMNativePortUpConverter code
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2020-05-11 16:47:43 +02:00 |
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Jędrzej Boczar
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2f35e9714d
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frontend/adaptation: fix error when read follows write to the same address
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2020-05-11 16:11:40 +02:00 |
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Jędrzej Boczar
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1587ee3611
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frontend/adaptation: use port.cmd.last instead of port.flush in up-converter
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2020-05-11 15:28:32 +02:00 |
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Jędrzej Boczar
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35fa91c055
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test/crossbar: up-conversion with mode="both" should be working now
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2020-05-11 14:56:39 +02:00 |
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Jędrzej Boczar
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9b90a56e07
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frontend/adaptation: combine read/write port up-converters and extend tests
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2020-05-11 14:56:39 +02:00 |
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Jędrzej Boczar
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762cd6d0f1
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test/adaptation: add port converter tests with mode="both"
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2020-05-11 14:56:39 +02:00 |
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Jędrzej Boczar
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7a0f7a7ead
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test/common: fix error in test data
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2020-05-11 14:56:39 +02:00 |
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Jędrzej Boczar
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1cc9656a2d
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test/crossbar: improve NativePortDriver to use separate generatos on data paths
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2020-05-11 14:25:06 +02:00 |
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Jędrzej Boczar
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025e280804
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test/crossbar: fix test that was not being run
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2020-05-11 14:25:06 +02:00 |
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Florent Kermarrec
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52b49fb80e
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test/reference: update.
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2020-05-09 18:02:42 +02:00 |
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Florent Kermarrec
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20a849c652
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test/reference: update ddr4_init.h
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2020-04-28 11:57:11 +02:00 |
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enjoy-digital
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cec3a994e8
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Merge pull request #181 from antmicro/jboc/eeprom-timings
Add option to load module data from DDR3 SPD EEPROM
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2020-04-25 08:25:35 +02:00 |
Jędrzej Boczar
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312bce2bf1
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modules: pass rate automatically when creating module from SPD data
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2020-04-17 14:14:02 +02:00 |
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Jędrzej Boczar
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07bbd79eaf
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modules: update existsing SO-DIMM timings based on SPD data
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2020-04-17 11:57:55 +02:00 |
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Florent Kermarrec
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d061e60611
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test/reference: update.
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2020-04-16 11:38:43 +02:00 |
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Jędrzej Boczar
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cf83ac6422
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test: improve SPD tests of Micron DDR3 SO-DIMM modules
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2020-04-16 10:57:09 +02:00 |
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Jędrzej Boczar
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854a614f99
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modules: fix calculations of speedgrade from tck in SPD data
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2020-04-16 10:12:23 +02:00 |
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Jędrzej Boczar
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3980e062d5
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modules: add option to load module parameters from SPD data
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2020-04-15 16:20:55 +02:00 |
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Florent Kermarrec
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de55a8e170
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test/test_bandwidth: review, cleanup, fix typo.
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2020-04-14 21:57:40 +02:00 |
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Florent Kermarrec
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907ef73971
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test/test_wishbone: add comments/cleanup.
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2020-04-14 21:48:44 +02:00 |
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Florent Kermarrec
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02fd39cf70
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test/test_fifo: add comments.
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2020-04-14 21:40:51 +02:00 |