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1498 Commits

Author SHA1 Message Date
Florent Kermarrec 39c0b0356c bench/uartbone: Update with LiteX change. 2023-07-20 15:44:18 +02:00
Florent Kermarrec b291032987 frontend/dma/LiteDRAMDMAReader: Simplify FIFO reservation and add last generation support. 
With this, last is now asserted on the last cycle of the DMA transfer, making behavior similar to WishboneDMAReader.

This is useful to create packets from DRAM data.
 2023-07-11 16:40:52 +02:00
Florent Kermarrec 0ba7da9ee9 core/bankmachine: Switch back to Replicate since Constant does not support 0-width. 2023-07-07 12:38:56 +02:00
Florent Kermarrec b148ade774 core/bankmachine: Minor cleanup on _AddressSlicer.col. 2023-07-07 09:56:15 +02:00
enjoy-digital 01355ff781
Merge pull request #313 from cklarhorst/master 
Add MT46H128M16 and change bankmaschine to not use A10 for col addresses.
 2023-07-07 08:53:25 +02:00
enjoy-digital 6f53acae22
Merge pull request #343 from trabucayre/fix_gw2ddrphy_import 
phy/gw2ddrphy: migen.genlib -> litex.gen.genlib (fix commit 6297370e3c)
 2023-07-07 08:50:25 +02:00
Florent Kermarrec 17ade2a512 ci: Use same fixed verilator commit than litex. 2023-07-07 08:46:20 +02:00
Gwenhael Goavec-Merou b8c7582274 phy/gw2ddrphy: migen.genlib -> litex.gen.genlib (fix commit 6297370e3c) 
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
 2023-07-07 07:46:32 +02:00
Florent Kermarrec 6297370e3c global: Switch to litex.gen.genlib.misc. 2023-07-06 22:06:16 +02:00
Hans Baier e446c06339
frontend/avalon: properly implement bursts (#340) 
frontend/avalon: properly implement bursts
 2023-05-31 08:14:52 +02:00
Chen 83a29b190d
Add support for clam shell topology (#332) 
Add clam shell topology support.
 2023-05-25 22:20:21 +02:00
Florent Kermarrec d8c327b2b1 ci: Increase similarities with LiteX CI. 2023-05-23 16:41:59 +02:00
Florent Kermarrec b452f09df6 frontend/avalon: Minor cosmetic fixes. 2023-05-23 14:57:36 +02:00
Hans Baier f1293eae1e
Avalon frontend for LiteDRAM (#337) 
Add initial Avalon MM frontend + tests.
 2023-05-23 14:52:05 +02:00
Florent Kermarrec d7df59560e setup.py: Prepare for 2023.04. 2023-05-07 20:47:47 +02:00
enjoy-digital e452da7a00
Merge pull request #330 from timkpaine/tkp/ci 
add manifest, uplift setup.py to pass twine checks
 2023-04-11 17:01:51 +02:00
Tim Paine ad00237fa2 fix typo in ci 2023-04-07 19:08:35 -04:00
Tim Paine 81203855a6 move up version 2023-04-07 19:06:45 -04:00
Tim Paine d7886c5fc5 add manifest, uplift setup.py to pass twine checks 2023-04-07 18:59:35 -04:00
enjoy-digital 6c8df7cc7b
Merge pull request #326 from trabucayre/gw2ddrphy_fix_warnings 
phy/gw2ddrphy: supressing warnings about unconnected and bit length.
 2023-02-08 19:12:01 +01:00
Gwenhael Goavec-Merou 895b653a96 phy/gw2ddrphy: supressing warnings about unconnected and bit length. 2023-02-08 18:26:54 +01:00
enjoy-digital 455305a3ed
Merge pull request #322 from antmicro/msieron/make-tests-parallel-safe 
Make tests safe to run in parallel
 2023-01-31 08:25:18 +01:00
Florent Kermarrec f94366c769 ci: Add help2man install for verilator compilation. 2023-01-20 19:14:17 +01:00
Florent Kermarrec 18f00151ed ci: Specify verilator sha1 (Build broken with recent versions). 2023-01-19 10:01:38 +01:00
Florent Kermarrec d95c1fc583 frontend/dma: Update omit signals in LiteDRAMDMAReader (Thanks @mohammadshahidzade). 2023-01-16 11:21:47 +01:00
Michal Sieron a912a88081 Make tests safe to run in parallel 
For example using pytest-parallel you can greatly reduce time it takes
to run all tests.

```
$ pytest --workers auto test
```

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-11 21:49:50 +01:00
enjoy-digital b749e10970
Merge pull request #321 from antmicro/msieron/sdram-hw-test 
frontend/bist: replicate LFSR output to fill the DRAM port
 2023-01-11 19:10:23 +01:00
Michal Sieron dad2c972f7 test/common: fix expected data for test_bist.py 
Expected data needs to be replicated to fill given data_width.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-11 17:13:52 +01:00
Michal Sieron 73c3ec6b68 frontend/bist: make LFSR output comb 
Otherwise first output after reset is 0.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-11 15:36:19 +01:00
Michal Sieron f466c5f1db frontend/bist: replicate LFSR output to fill DRAM port 
Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-11 15:36:19 +01:00
Michal Sieron 89581c1da7 gen: increase ROM size 
Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-11 15:36:19 +01:00
Florent Kermarrec 69b401dea1 test/test_init: Update. 2023-01-10 14:45:27 +01:00
enjoy-digital d17b021aa2
Merge pull request #320 from antmicro/msieron/sdram-spd 
init: Define `SDRAM_PHY_[DDR3|DDR4|...]` and `SDRAM_PHY_SUPPORTED_MEMORY`
 2023-01-10 09:39:12 +01:00
Michal Sieron 8fa325310a init: define SDRAM_PHY_SUPPORTED_MEMORY 
To use as a default value when one can't read SDRAM size from the SPD.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-09 16:03:09 +01:00
Michal Sieron 4c9f184566 init: define SDRAM_PHY_[DDR3|DDR4|...] 
Will allow to ifdef code specific to some memory types like SPD reads.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-09 16:03:09 +01:00
enjoy-digital 8339f54322
Merge pull request #319 from antmicro/msieron/fix-bist-errors 
frontend/bist: properly signal finished writes
 2023-01-05 22:21:23 +01:00
Michal Sieron f45ca410ad frontend/bist: properly signal finished writes 
Without it, software was resetting the generator too early and wrong
data was being written to the RAM.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2023-01-04 14:00:59 +01:00
Florent Kermarrec 3b2bcf91ed ci: Switch to ubuntu 22.04 and increase similarities with LiteX's CI. 2022-12-09 11:06:58 +01:00
Florent Kermarrec 6b00d1adce ci: Install RISC-V GCC with litex_setup.py. 2022-12-08 21:57:50 +01:00
Florent Kermarrec 379db85fc7 bench: Update with LiteX/LiteX-Boards changes. 2022-12-08 10:29:43 +01:00
enjoy-digital 1f1ab2d3ea
Merge pull request #314 from antmicro/msieron/fix-ddr4-sim 
Fix DFITimingsChecker for DDR4 simulation
 2022-11-18 12:47:13 +01:00
Michal Sieron f25604c153 Fix DFITimingsChecker for DDR4 simulation 
In case of DDR4 tRFC and tREFI timings are actually dictionaries with
timings specific for the chosen refresh mode.

Right now, it is impossible to simulate DDR4, because an exception
happens in `DFITimingsChecker.prepare_timings` method when indexing
`val` variable.

This is due to the fact, that in `DFITimingsChecker.__init__` we request
timing values from the module by name, ignoring the fact that some of
them (tRFC and tREFI) need to be first accessed using the chosen refresh
mode.

This commit fixes this error, by properly using `key` parameter when
calling `SDRAMModule.get` method to get only required timing.

If one were to fix it in `DFITimingsChecker.prepare_timings` method,
it would require duplicating logic from `SDRAMModule.get` so this is a
simpler and cleaner solution.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
 2022-11-14 21:36:17 +01:00
Christian Klarhorst cf893a9839 Bankmaschine: Don't use A10 for col addresses. 
A10 is reserved for auto precharge.
For memories with more than 1024 cols (>10bit) A[0:9] and A[11:] is used.

I tested this with MT46H128M16.
 2022-10-31 10:08:48 +01:00
Christian Klarhorst 4815be2fef Add new module MT46H128M16 2022-10-30 10:18:49 +01:00
Florent Kermarrec c770dd62ed test/test_lpddr5: Add tINIT2 as allowed warning. 2022-10-25 08:58:20 +02:00
Florent Kermarrec d1529d7508 ci: Bump to ubuntu 20.04. 2022-10-14 18:17:02 +02:00
Florent Kermarrec ae0763e252 axi: Update frontend/test with LiteX changes. 2022-09-15 17:52:01 +02:00
Florent Kermarrec 559dd24c99 phy/gw2ddrphy: Minor cosmetic cleanups. 2022-09-08 16:09:38 +02:00
Florent Kermarrec cff8500f52 phy/gw2ddrphy: Add explicit TXCLK_POL and set it to 1 for DQS. 2022-09-08 16:03:39 +02:00
Florent Kermarrec 5b72d1a34a gw2ddrphy: Add TCLK_SOURCE on DQS's OSER4_MEM. 2022-09-08 10:49:54 +02:00