Florent Kermarrec
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c4161cfbfe
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examples: update sim
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2019-03-15 20:16:42 +01:00 |
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Florent Kermarrec
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640194a5c9
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examples: add nexys4ddr_config
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2019-02-21 23:32:45 +01:00 |
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Florent Kermarrec
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0ac1af367a
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examples/litedram_gen: add DDR2 support
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2019-02-21 23:32:23 +01:00 |
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Florent Kermarrec
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f4184ec37a
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example/litedram_gen: update, add descriptions of config parameters
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2019-02-21 23:19:52 +01:00 |
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Florent Kermarrec
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bc6a3f220a
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examples/sim/sim/py: remove apb interface
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2018-11-17 09:30:58 +01:00 |
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Florent Kermarrec
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e7e4bc527f
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examples/sim: add ddr3 micron model
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2018-11-17 09:20:34 +01:00 |
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Florent Kermarrec
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f219693635
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examples: add simulation
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2018-11-17 09:19:52 +01:00 |
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Florent Kermarrec
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f11506accd
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examples/litedram_gen: cleanup pins definition
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2018-10-15 09:38:34 +02:00 |
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Florent Kermarrec
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0f46dc4ab7
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modules: add DDR3-800 timings for MT41J128M16 and use it on arty example
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2018-10-01 11:59:54 +02:00 |
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Florent Kermarrec
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426ae23d2a
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examples/litedram_gen: add sdram_module_speedgrade parameter
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2018-10-01 11:48:15 +02:00 |
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Florent Kermarrec
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30c32f557c
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example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :)
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2018-09-25 10:40:24 +02:00 |
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Florent Kermarrec
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37f1decfb2
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multirank: one cs_n/cke/odt/clk per rank
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2018-09-09 14:32:15 +02:00 |
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Florent Kermarrec
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8ddc6c735d
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drive odt of all ranks, fixes and test non regression with 1 rank
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2018-09-09 01:52:24 +02:00 |
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Florent Kermarrec
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cc481be81f
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examples: add sdram_rank_nb and user_ports_id_width
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2018-09-07 17:55:46 +02:00 |
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Florent Kermarrec
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1652ab95c8
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examples/litedram_gen: fix address width of axi ports (addressing in bytes not words)
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2018-09-05 09:13:47 +02:00 |
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Florent Kermarrec
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1e64b7f492
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examples/litedram_gen: expose resp signals to user
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2018-09-05 08:51:27 +02:00 |
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Florent Kermarrec
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de69867995
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examples/litedram_gen: expose last signals to user
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2018-09-05 08:32:49 +02:00 |
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Florent Kermarrec
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e8bd782999
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examples/litedram_gen: expose burst signals to user
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2018-09-05 08:31:57 +02:00 |
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Florent Kermarrec
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5e4dca9a7b
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add examples with standalone cores for arty and genesys2
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2018-08-31 23:20:47 +02:00 |