Commit Graph

8 Commits

Author SHA1 Message Date
Gabriel L. Somlo 65451f426a examples/litedram_gen: allow direct access to CSR (I/O) registers
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
[florent@enjoy-digital.fr: use add_csr_master, fix csr_port.dat_r typo]
2019-05-16 15:05:30 -04:00
Florent Kermarrec 0ac1af367a examples/litedram_gen: add DDR2 support 2019-02-21 23:32:23 +01:00
Florent Kermarrec f4184ec37a example/litedram_gen: update, add descriptions of config parameters 2019-02-21 23:19:52 +01:00
Florent Kermarrec 0f46dc4ab7 modules: add DDR3-800 timings for MT41J128M16 and use it on arty example 2018-10-01 11:59:54 +02:00
Florent Kermarrec 426ae23d2a examples/litedram_gen: add sdram_module_speedgrade parameter 2018-10-01 11:48:15 +02:00
Florent Kermarrec 30c32f557c example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :) 2018-09-25 10:40:24 +02:00
Florent Kermarrec cc481be81f examples: add sdram_rank_nb and user_ports_id_width 2018-09-07 17:55:46 +02:00
Florent Kermarrec 5e4dca9a7b add examples with standalone cores for arty and genesys2 2018-08-31 23:20:47 +02:00