7b3c6abd50
litedram/frontend/adapter.py rewrite up converter to optimize for bandwidth
...
This change is necessary to run litevideo, as old up converter was too slow to support
high bandwidth requirements of HDMI core.
Also old upconverter had two bugs:
* reading sequentially and non-sequentially would return data in the same order
* writing sequentailly and non-sequentially would return different memory state
test/test_adapter.py add new up converter test: test_up_converter_writes_not_sequential
This test checks if non-sequential writes to one dram word will create the same result as sequential writes
Add parameters for rx_buffer, tx_buffer and cmd_buffer depths
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2022-06-27 17:49:31 +02:00
d95212bf0b
test: check converters at higher data width ratios
2021-09-01 14:59:05 +02:00
ac825e5112
add SPDX License identifier to header and specify file is part of LiteDRAM.
2020-08-23 15:52:08 +02:00
22bd01c014
frontend/wishbone: simplify by reusing LiteDRAMNativePortConverter
2020-05-13 17:14:42 +02:00
1587ee3611
frontend/adaptation: use port.cmd.last instead of port.flush in up-converter
2020-05-11 15:28:32 +02:00
9b90a56e07
frontend/adaptation: combine read/write port up-converters and extend tests
2020-05-11 14:56:39 +02:00
7a0f7a7ead
test/common: fix error in test data
2020-05-11 14:56:39 +02:00
1cc9656a2d
test/crossbar: improve NativePortDriver to use separate generatos on data paths
2020-05-11 14:25:06 +02:00
966ebcbc41
test: cleanup/uniformize things between tests.
2020-04-13 19:38:29 +02:00
8a0bcb3a2a
test: add core.crossbar tests
2020-04-10 12:46:10 +02:00
00fcdf6da7
test: split core.multiplexer tests into separate files
2020-04-01 15:36:14 +02:00
1f8868e6e9
test: add frontend.adaptation tests for different conversion ratios
2020-03-24 11:12:11 +01:00
f19d92b67f
test: add wishbone tests with data width mismatch
2020-03-20 14:48:50 +01:00
3c0fdf0710
test: handle 'we' in DRAMMemory, add memory debug messages
2020-03-20 14:48:39 +01:00
03f93998b5
test: move DMA specific tests to test_dma.py
2020-03-19 09:13:28 +01:00
9584c2fe88
test: remove use of rand_wait, rename rand_level to random
2019-07-23 21:14:17 +02:00
f018c9e268
add CONTRIBUTORS file and add copyright header to all files.
2019-06-23 23:59:10 +02:00
429d3a89de
test/common: set rdata_valid_rand_level default value to 0
2019-01-21 16:54:23 +01:00
7ef4869db9
test/test_axi: also add randomness on rdata.valid and wdata.ready
2018-11-30 11:22:04 +01:00
1fa73e4718
test: update
2018-09-06 11:10:45 +02:00
95cb7cdba5
test: rename read/write generators to handlers
2018-08-28 13:40:50 +02:00
10229d1e7d
test/test_axi: improve test_axi2native
2018-08-28 13:39:11 +02:00
6a46ea3052
test/test_bist: add generator test, remove async test
2018-08-28 11:50:11 +02:00
697f46a97f
replace litex.gen imports with migen imports
2018-02-23 13:39:23 +01:00
99550968e7
test: move BISTDriver to common and use it in test_bist_async
2017-01-17 15:18:10 +01:00
c56f90e865
test/test_bist: simplify and test modules directly not through CSR
2017-01-17 14:14:50 +01:00
aac61f346e
test: start fixing bist_tb
2016-12-17 19:24:12 +01:00
e21b45b608
Merge remote-tracking branch 'upstream/master' into bist
2016-12-17 18:15:59 +01:00
f1ad8991a4
bist: Working on improving the names of things.
2016-12-17 14:09:50 +01:00
8ff2f8779b
bist: Adding "halt on error" functionality.
...
Also include ability to see address of error and expected verse actual
data values.
Extend the test bench to test this functionality.
2016-12-17 14:09:50 +01:00
da144f41d4
bist: Refactoring test bench.
...
Move a bunch of common code into common.py
2016-12-17 14:09:50 +01:00
e2b6bda7d0
test: add random and autocheck on downconverter_tb and upconverter_tb
2016-06-08 17:33:21 +02:00
3fe3a843e0
test: also test reads on downconverter/upconverter
2016-05-24 21:40:46 +02:00
de61cefb58
test: add downconverter_tb and some fixes
2016-05-24 20:48:26 +02:00
f36c65b66f
test: move DRAMMemory model to common
2016-05-23 13:30:38 +02:00
d7458a3c34
test: remove common
2016-05-04 01:16:29 +02:00
7732ff27a6
update code, start bankmachine refactoring and remove old code (will be rewritten)
2015-09-15 10:22:39 +02:00
Maciej Dudek
Jędrzej Boczar
Florent Kermarrec
Jędrzej Boczar
Tim 'mithro' Ansell