Commit graph

1389 commits

Author SHA1 Message Date
Christian Klarhorst
8226dca898 add LPDDR module 2021-11-25 14:18:05 +01:00
enjoy-digital
78ff236ca7
Merge pull request from antmicro/add-rdimms
modules: add other RDIMM modules
2021-11-06 08:30:41 +01:00
enjoy-digital
0eb59ebe88
Merge pull request from hansfbaier/master
W9825G6KH6 seems to use 8192 refresh cycles not 8000
2021-11-06 08:30:09 +01:00
Hans Baier
c3ec0ab079 W9825G6KH6 seems to use 8192 refresh cycles not 8000 2021-11-06 07:48:06 +07:00
Alessandro Comodi
021f243f6d modules: add other RDIMM modules
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-11-04 14:23:13 +01:00
Florent Kermarrec
3d1d711a43 modules/W9825G6KH6: Avoid specific comments/code.
We have to keep things simple and avoid specific code preventing maintenance/evolutions.
2021-11-01 23:03:34 +01:00
enjoy-digital
bf7c06371f
Merge pull request from hansfbaier/master
add support for Winbond W9825G6KH-6 at 50MHz 1:2 rate
2021-11-01 22:58:25 +01:00
enjoy-digital
cea9d00d20
Merge pull request from antmicro/jboc/lpddr5-rebase
LPDDR5 support
2021-11-01 22:18:38 +01:00
enjoy-digital
3b47170a0c
Merge pull request from antmicro/rpc-dram-support
Add RPC DRAM support
2021-11-01 21:52:36 +01:00
Florent Kermarrec
bf9b3609d9 frontend/fifo/LiteDRAMFIFO: Describe parameters. 2021-11-01 21:46:39 +01:00
Florent Kermarrec
a8afbe8b08 test/test_refresh: Update. 2021-11-01 15:33:21 +01:00
Florent Kermarrec
5d7adcfa7c core/refresher: Add assert on clk_freq/tREFI ratio.
Prevent generating a controller with tREFI too low to accept any transaction.
2021-11-01 14:58:41 +01:00
Jean-François Nguyen
5aad6cd3d1 gen: use sys_clk_freq for SDRAMPHYModel timings, instead of 100MHz. 2021-11-01 14:28:19 +01:00
Alessandro Comodi
c7721c4b93 ci: build and install latest verilator
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:40:02 +02:00
Alessandro Comodi
f8ac00a8ab lpddr5: sim: add write leveling step as well
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:22:30 +02:00
Alessandro Comodi
d7e2c82795 lpddr5: sim: fix non-syncronized pipe in simulation
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:22:30 +02:00
Alessandro Comodi
50ba27eb4c lpddr5: tests: add additional initial tCK delay for bitslip
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:22:30 +02:00
Alessandro Comodi
ab130e170a lpddr5: add write leveling support
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:22:30 +02:00
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ed6c7759b5 phy/lpddr5/sim: fix double reset with check_timings=False at high frequency 2021-10-26 12:22:30 +02:00
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43aef6255e phy/lpddr5: add Verilator tests 2021-10-26 12:22:30 +02:00
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2989963b9c phy: move regex pattern for parsing SimLogger logs to SimLogger class 2021-10-26 12:22:30 +02:00
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aad7cce8c5 phy/lpddr5/simphy: use the same serialization scheme in S7 PHY to serve as reference 2021-10-26 12:22:30 +02:00
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6b2a1bc47c phy/lpddr5/s7phy: apply command serialization fixes 2021-10-26 12:22:30 +02:00
Alessandro Comodi
abc77f367c lpddr5: wck sync: fix syncing and adjusted unit tests
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:22:30 +02:00
Alessandro Comodi
c4273146c1 lpddr5: wck sync: adapt tests as now wck sync is required
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:22:30 +02:00
Alessandro Comodi
c9954744df lpddr5: wck sync at every transaction
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:22:30 +02:00
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95be0be69d phy/lpddr5/sim: fix incorrect write latency in DRAM simulator 2021-10-26 12:22:30 +02:00
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8c10f1405b phy/lpddr5: delay WCK sync FSM transition by 1 cycle
With fixed serialization logic WCK sync can be now started later
which avoids the need for special logic when tWCKENL=0.
2021-10-26 12:22:30 +02:00
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32a56ffe28 phy/lpddr5: fix command serialization 2021-10-26 12:22:30 +02:00
Alessandro Comodi
05c0720ae2 lpddr5: add MR28 init default config
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:22:30 +02:00
Alessandro Comodi
d98b5703fc lpddr5: commands: handle ZQC MPC command
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:22:30 +02:00
Piotr Binkowski
d496bd22e5 init: add lpddr5 write leveling settings 2021-10-26 12:22:30 +02:00
Piotr Binkowski
2c2b73442a phy/lpddr5: add PHY for series 7 2021-10-26 12:22:30 +02:00
Piotr Binkowski
e4e2aa49b8 phy/lpddr4: extract io helpers to a separate class 2021-10-26 12:22:30 +02:00
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a4fb1a633a phy/lpddr5: do not use dataclasses for Python 3.6 compatibility 2021-10-26 12:22:30 +02:00
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9795d6902c phy/lpddr5/sim: partially disable DFITimingsChecker when --disable-delay is on
With --disable-delay the software won't insert delays in between
commands during memory training which results in DFITimingsChecker
reporting timing violations. With this change we disable
DFITimingsChecker until software completes memory initialization.
2021-10-26 12:22:30 +02:00
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247641a353 phy/lpddr5/sim: don't check timings when --disable-delay is used 2021-10-26 12:22:30 +02:00
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0009f6d2be phy/lpddr5/sim: show timing progress when logging timing violation 2021-10-26 12:22:30 +02:00
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9ef6e4b444 phy/lpddr5/sim: add DFITimingsChecker 2021-10-26 12:22:30 +02:00
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91f14b2414 phy/lpddr5/sim: add option to wrap the PHY with DFIRateConverter 2021-10-26 12:22:30 +02:00
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e329545ea6 phy/lpddr5/sim: make wr/rd timings correct for both CKR=4 and 2 2021-10-26 12:22:30 +02:00
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2c8a06ed00 phy/lpddr5/sim: reset FSM to initial state when RESET_n is pulled low 2021-10-26 12:22:30 +02:00
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59467f8ae6 phy/lpddr5: add a way to send actual NOP instead of DESELECT 2021-10-26 12:22:30 +02:00
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9c49d80e6b phy/lpddr5: add power-up initialization sequence 2021-10-26 12:22:30 +02:00
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c795bafda7 phy/lpddr5/sim: add verification of initialization sequence 2021-10-26 12:22:30 +02:00
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27da8c5c43 phy/lpddr5/sim: update mode register reset values 2021-10-26 12:22:30 +02:00
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e39aec4b7e phy/lpddr5/sim: fix command timeouts calculation 2021-10-26 12:22:30 +02:00
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7f742c7fde phy/lpddr5/sim: handle data masking during masked-write 2021-10-26 12:22:30 +02:00
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26cbb700bc phy/lpddr5/sim: update delay for read data, add basic CAS handler 2021-10-26 12:22:30 +02:00
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4e974738d1 phy/lpddr5: fix column address encoding/decoding 2021-10-26 12:22:30 +02:00