8ed232f8dc
setup.py: Bump to 2023.12 to prepare release.
2023-12-25 15:33:14 +01:00
b55cd3d481
setup.py: Switch minimum Python version to 3.7 (To allow more than 255 arguents in functions).
2023-12-19 10:23:39 +01:00
6615941f0c
setup.py: Specify UTF-8 encoding for long_description/README.md.
2023-12-19 10:12:09 +01:00
3b4cb273ac
setup.py: Improve indentation.
2023-12-19 09:10:53 +01:00
e835544d95
CONTRIBUTORS: Update.
2023-11-10 10:40:24 +01:00
bacaae377a
README.md: Update.
2023-11-10 10:30:02 +01:00
16eb5a931c
Merge pull request #351 from trabucayre/gw5a_ddr3
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phy/gw5ddrphy: introducing GW5A DDR phy
2023-11-09 11:43:26 +01:00
da78fca00e
phy/gw5ddrphy: introducing GW5A DDR phy
2023-11-09 11:42:48 +01:00
e1434fa5c8
Merge pull request #350 from hansfbaier/master
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Add W9812G6JB SDRAM module
2023-11-09 08:21:57 +01:00
9cffe392ea
add W9812G6JB SDRAM module
2023-11-09 10:28:39 +07:00
4dec115023
setup.py: Update to 2023.08.
2023-09-18 08:40:57 +02:00
ed81c8cc86
phy/gw2ddrphy: Remove CHECKME now that working.
2023-08-29 16:48:10 +02:00
50fc6792e6
litedram/init: Cleanup supported memory generation.
2023-08-29 16:42:42 +02:00
6dadc11b21
phy/gw2ddrphy: fix cl/cwl latencies
2023-08-25 17:52:05 +02:00
afdf1aff43
phy: Remove useless WaitTimer imports.
2023-08-01 14:40:48 +02:00
39c0b0356c
bench/uartbone: Update with LiteX change.
2023-07-20 15:44:18 +02:00
b291032987
frontend/dma/LiteDRAMDMAReader: Simplify FIFO reservation and add last generation support.
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With this, last is now asserted on the last cycle of the DMA transfer, making behavior similar to WishboneDMAReader.
This is useful to create packets from DRAM data.
2023-07-11 16:40:52 +02:00
0ba7da9ee9
core/bankmachine: Switch back to Replicate since Constant does not support 0-width.
2023-07-07 12:38:56 +02:00
b148ade774
core/bankmachine: Minor cleanup on _AddressSlicer.col.
2023-07-07 09:56:15 +02:00
01355ff781
Merge pull request #313 from cklarhorst/master
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Add MT46H128M16 and change bankmaschine to not use A10 for col addresses.
2023-07-07 08:53:25 +02:00
6f53acae22
Merge pull request #343 from trabucayre/fix_gw2ddrphy_import
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phy/gw2ddrphy: migen.genlib -> litex.gen.genlib (fix commit 6297370e3c
2023-07-07 08:50:25 +02:00
17ade2a512
ci: Use same fixed verilator commit than litex.
2023-07-07 08:46:20 +02:00
b8c7582274
phy/gw2ddrphy: migen.genlib -> litex.gen.genlib (fix commit 6297370e3c)
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Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
2023-07-07 07:46:32 +02:00
6297370e3c
global: Switch to litex.gen.genlib.misc.
2023-07-06 22:06:16 +02:00
e446c06339
frontend/avalon: properly implement bursts ( #340 )
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frontend/avalon: properly implement bursts
2023-05-31 08:14:52 +02:00
83a29b190d
Add support for clam shell topology ( #332 )
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Add clam shell topology support.
2023-05-25 22:20:21 +02:00
d8c327b2b1
ci: Increase similarities with LiteX CI.
2023-05-23 16:41:59 +02:00
b452f09df6
frontend/avalon: Minor cosmetic fixes.
2023-05-23 14:57:36 +02:00
f1293eae1e
Avalon frontend for LiteDRAM ( #337 )
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Add initial Avalon MM frontend + tests.
2023-05-23 14:52:05 +02:00
d7df59560e
setup.py: Prepare for 2023.04.
2023-05-07 20:47:47 +02:00
e452da7a00
Merge pull request #330 from timkpaine/tkp/ci
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add manifest, uplift setup.py to pass twine checks
2023-04-11 17:01:51 +02:00
ad00237fa2
fix typo in ci
2023-04-07 19:08:35 -04:00
81203855a6
move up version
2023-04-07 19:06:45 -04:00
d7886c5fc5
add manifest, uplift setup.py to pass twine checks
2023-04-07 18:59:35 -04:00
6c8df7cc7b
Merge pull request #326 from trabucayre/gw2ddrphy_fix_warnings
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phy/gw2ddrphy: supressing warnings about unconnected and bit length.
2023-02-08 19:12:01 +01:00
895b653a96
phy/gw2ddrphy: supressing warnings about unconnected and bit length.
2023-02-08 18:26:54 +01:00
455305a3ed
Merge pull request #322 from antmicro/msieron/make-tests-parallel-safe
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Make tests safe to run in parallel
2023-01-31 08:25:18 +01:00
f94366c769
ci: Add help2man install for verilator compilation.
2023-01-20 19:14:17 +01:00
18f00151ed
ci: Specify verilator sha1 (Build broken with recent versions).
2023-01-19 10:01:38 +01:00
d95c1fc583
frontend/dma: Update omit signals in LiteDRAMDMAReader (Thanks @mohammadshahidzade).
2023-01-16 11:21:47 +01:00
a912a88081
Make tests safe to run in parallel
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For example using pytest-parallel you can greatly reduce time it takes
to run all tests.
```
$ pytest --workers auto test
```
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-11 21:49:50 +01:00
b749e10970
Merge pull request #321 from antmicro/msieron/sdram-hw-test
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frontend/bist: replicate LFSR output to fill the DRAM port
2023-01-11 19:10:23 +01:00
dad2c972f7
test/common: fix expected data for test_bist.py
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Expected data needs to be replicated to fill given data_width.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-11 17:13:52 +01:00
73c3ec6b68
frontend/bist: make LFSR output comb
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Otherwise first output after reset is 0.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-11 15:36:19 +01:00
f466c5f1db
frontend/bist: replicate LFSR output to fill DRAM port
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Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-11 15:36:19 +01:00
89581c1da7
gen: increase ROM size
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Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-11 15:36:19 +01:00
69b401dea1
test/test_init: Update.
2023-01-10 14:45:27 +01:00
d17b021aa2
Merge pull request #320 from antmicro/msieron/sdram-spd
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init: Define `SDRAM_PHY_[DDR3|DDR4|...]` and `SDRAM_PHY_SUPPORTED_MEMORY`
2023-01-10 09:39:12 +01:00
8fa325310a
init: define SDRAM_PHY_SUPPORTED_MEMORY
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To use as a default value when one can't read SDRAM size from the SPD.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-09 16:03:09 +01:00
4c9f184566
init: define SDRAM_PHY_[DDR3|DDR4|...]
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Will allow to ifdef code specific to some memory types like SPD reads.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-09 16:03:09 +01:00
Florent Kermarrec
Gwenhael Goavec-Merou
Hans Baier
Gwenhael Goavec-Merou
Chen
Tim Paine
Michal Sieron