367231322d
litedram_gen: Add pll_locked to ECP5
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Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
2021-11-03 14:06:26 +08:00
3d1d711a43
modules/W9825G6KH6: Avoid specific comments/code.
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We have to keep things simple and avoid specific code preventing maintenance/evolutions.
2021-11-01 23:03:34 +01:00
bf7c06371f
Merge pull request #245 from hansfbaier/master
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add support for Winbond W9825G6KH-6 at 50MHz 1:2 rate
2021-11-01 22:58:25 +01:00
cea9d00d20
Merge pull request #270 from antmicro/jboc/lpddr5-rebase
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LPDDR5 support
2021-11-01 22:18:38 +01:00
3b47170a0c
Merge pull request #273 from antmicro/rpc-dram-support
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Add RPC DRAM support
2021-11-01 21:52:36 +01:00
bf9b3609d9
frontend/fifo/LiteDRAMFIFO: Describe parameters.
2021-11-01 21:46:39 +01:00
a8afbe8b08
test/test_refresh: Update.
2021-11-01 15:33:21 +01:00
5d7adcfa7c
core/refresher: Add assert on clk_freq/tREFI ratio.
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Prevent generating a controller with tREFI too low to accept any transaction.
2021-11-01 14:58:41 +01:00
5aad6cd3d1
gen: use sys_clk_freq for SDRAMPHYModel timings, instead of 100MHz.
2021-11-01 14:28:19 +01:00
c7721c4b93
ci: build and install latest verilator
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:40:02 +02:00
f8ac00a8ab
lpddr5: sim: add write leveling step as well
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:22:30 +02:00
d7e2c82795
lpddr5: sim: fix non-syncronized pipe in simulation
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:22:30 +02:00
50ba27eb4c
lpddr5: tests: add additional initial tCK delay for bitslip
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:22:30 +02:00
ab130e170a
lpddr5: add write leveling support
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:22:30 +02:00
ed6c7759b5
phy/lpddr5/sim: fix double reset with check_timings=False at high frequency
2021-10-26 12:22:30 +02:00
43aef6255e
phy/lpddr5: add Verilator tests
2021-10-26 12:22:30 +02:00
2989963b9c
phy: move regex pattern for parsing SimLogger logs to SimLogger class
2021-10-26 12:22:30 +02:00
aad7cce8c5
phy/lpddr5/simphy: use the same serialization scheme in S7 PHY to serve as reference
2021-10-26 12:22:30 +02:00
6b2a1bc47c
phy/lpddr5/s7phy: apply command serialization fixes
2021-10-26 12:22:30 +02:00
abc77f367c
lpddr5: wck sync: fix syncing and adjusted unit tests
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:22:30 +02:00
c4273146c1
lpddr5: wck sync: adapt tests as now wck sync is required
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:22:30 +02:00
c9954744df
lpddr5: wck sync at every transaction
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:22:30 +02:00
95be0be69d
phy/lpddr5/sim: fix incorrect write latency in DRAM simulator
2021-10-26 12:22:30 +02:00
8c10f1405b
phy/lpddr5: delay WCK sync FSM transition by 1 cycle
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With fixed serialization logic WCK sync can be now started later
which avoids the need for special logic when tWCKENL=0.
2021-10-26 12:22:30 +02:00
32a56ffe28
phy/lpddr5: fix command serialization
2021-10-26 12:22:30 +02:00
05c0720ae2
lpddr5: add MR28 init default config
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:22:30 +02:00
d98b5703fc
lpddr5: commands: handle ZQC MPC command
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:22:30 +02:00
d496bd22e5
init: add lpddr5 write leveling settings
2021-10-26 12:22:30 +02:00
2c2b73442a
phy/lpddr5: add PHY for series 7
2021-10-26 12:22:30 +02:00
e4e2aa49b8
phy/lpddr4: extract io helpers to a separate class
2021-10-26 12:22:30 +02:00
a4fb1a633a
phy/lpddr5: do not use dataclasses for Python 3.6 compatibility
2021-10-26 12:22:30 +02:00
9795d6902c
phy/lpddr5/sim: partially disable DFITimingsChecker when --disable-delay is on
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With --disable-delay the software won't insert delays in between
commands during memory training which results in DFITimingsChecker
reporting timing violations. With this change we disable
DFITimingsChecker until software completes memory initialization.
2021-10-26 12:22:30 +02:00
247641a353
phy/lpddr5/sim: don't check timings when --disable-delay is used
2021-10-26 12:22:30 +02:00
0009f6d2be
phy/lpddr5/sim: show timing progress when logging timing violation
2021-10-26 12:22:30 +02:00
9ef6e4b444
phy/lpddr5/sim: add DFITimingsChecker
2021-10-26 12:22:30 +02:00
91f14b2414
phy/lpddr5/sim: add option to wrap the PHY with DFIRateConverter
2021-10-26 12:22:30 +02:00
e329545ea6
phy/lpddr5/sim: make wr/rd timings correct for both CKR=4 and 2
2021-10-26 12:22:30 +02:00
2c8a06ed00
phy/lpddr5/sim: reset FSM to initial state when RESET_n is pulled low
2021-10-26 12:22:30 +02:00
59467f8ae6
phy/lpddr5: add a way to send actual NOP instead of DESELECT
2021-10-26 12:22:30 +02:00
9c49d80e6b
phy/lpddr5: add power-up initialization sequence
2021-10-26 12:22:30 +02:00
c795bafda7
phy/lpddr5/sim: add verification of initialization sequence
2021-10-26 12:22:30 +02:00
27da8c5c43
phy/lpddr5/sim: update mode register reset values
2021-10-26 12:22:30 +02:00
e39aec4b7e
phy/lpddr5/sim: fix command timeouts calculation
2021-10-26 12:22:30 +02:00
7f742c7fde
phy/lpddr5/sim: handle data masking during masked-write
2021-10-26 12:22:30 +02:00
26cbb700bc
phy/lpddr5/sim: update delay for read data, add basic CAS handler
2021-10-26 12:22:30 +02:00
4e974738d1
phy/lpddr5: fix column address encoding/decoding
2021-10-26 12:22:30 +02:00
a015b66e4f
phy/lpddr5: fix write latency
2021-10-26 12:22:30 +02:00
e906c82ea2
phy/lpddr5/sim: debug serialization in gtkwave savefile
2021-10-26 12:22:30 +02:00
bfb8aaf44c
phy/lpddr5/sim: clean up write burst handling and implement read bursts
2021-10-26 12:22:30 +02:00
b8616fdfac
phy/lpddr5/sim: make adding module loggers simpler
2021-10-26 12:22:30 +02:00
Matt Johnston
Florent Kermarrec
Jean-François Nguyen
Alessandro Comodi
Jędrzej Boczar
Piotr Binkowski