ac4b339a6f
test/reference: update init headers
2019-11-15 19:45:39 +01:00
3fa4397224
Merge pull request #95 from gsomlo/gls-dfii-nphases
...
init: improve legibility of generated/sdram_phy.h (cosmetic)
2019-11-15 19:42:27 +01:00
bdcecad76f
init: improve legibility of generated/sdram_phy.h (cosmetic)
...
Use DFII_NPHASES constant (defined earlier in the file) to size the
two 'sdram_dfii_pix_[wrdata|rddata]_addr' arrays, instead of a bare
number. Additionally, ensure the first array element is indented by
a tab, same as the ones following it.
2019-11-12 14:06:47 -05:00
08325dd04e
Merge pull request #94 from mithro/lpddr-fix
...
Fix broken LPDDR support.
2019-10-30 14:28:53 -07:00
746329cb43
Fix broken lpddr support.
...
Fixes #93 .
2019-10-30 13:51:05 -07:00
401554f94c
Merge pull request #92 from gsomlo/gls-assert-width
...
frontend/[axi,wishbone]: add data_width match assertion, add base_address to LiteDRAMWishbone2Native
2019-10-25 12:25:07 +02:00
7356d3b15d
frontend/wishbone: add base_address param. to LiteDRAMWishbone2Native
2019-10-24 11:31:56 -04:00
24203cfc7b
frontend/axi: add assertion on matching axi, native port data_width
2019-10-23 10:01:42 -04:00
d84e1b4ac5
frontend/axi: add assert on axi.address_width and base_address
2019-10-18 18:30:39 +02:00
1d037d2a64
frontend/axi: add base_address parameter to LiteDRAMAXI2Native
2019-10-17 12:16:15 +02:00
5d1a9847aa
core: add LiteDRAMCore (ControllerInjector from LiteX)
2019-09-29 14:42:41 +02:00
d647abd026
gen: fix with_wishbone
2019-09-23 15:54:53 +02:00
db97203877
gen: use SoCCore with_wishbone parameter, do more replace in yml files before passing config to LiteDRAMCore
2019-09-23 12:55:14 +02:00
adf481f1d5
gen: disable peripherals that are not used when cpu_type is None
2019-09-23 10:16:47 +02:00
233191939e
gen: change CSR config names, switch to csr_expose/csr_align
2019-09-23 09:12:40 +02:00
da408a3982
gen: fix default csr_port_align value
2019-09-23 09:05:54 +02:00
bac66aa08f
gen: In conjunction with the corresponding changes in litex itself, this will allow us to generate a more useful standalone litedram core.
...
The CSR alignment and base can be specified (which mostly affects
the generation of csr.h) andwe stop trying to copy the init code
that we haven't generated
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-23 08:58:16 +02:00
afbf709767
We had the address and data bus sizes mixed up
...
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-23 08:51:04 +02:00
d93dded624
frontend/wishbone: add data_width assertions
2019-09-18 21:12:23 +02:00
f586aada1c
phys: improve presentation (add separators, better indent)
2019-09-11 09:50:46 +02:00
783258c97f
phys: use dfi instead if self.dfi internally
2019-09-11 09:00:36 +02:00
59c1289432
phy/usddrphy: move DDR4DFIMux to dfi.py
2019-09-11 08:57:58 +02:00
f861d99903
core/refresher: improve naming/parameters of refresh postponing
2019-09-11 08:38:22 +02:00
dc1bb53a88
phys: move get_cl_cw/get_sys_latency/get_sys_phases helpers to common
2019-09-11 08:00:54 +02:00
509f60652a
README: add periodic refresh/ZQ short calibration.
2019-09-09 18:05:17 +02:00
40b4c62889
test/test_init: fix
2019-09-09 15:17:43 +02:00
5b48eb278a
test/test_init: delete generated file
2019-09-09 15:08:01 +02:00
188b6a8feb
add ZQ periodic short calibration support (default to 1s)
2019-09-09 15:07:38 +02:00
6e176d40ac
init: split by memtype
2019-09-09 12:10:48 +02:00
0b24b817e3
test: add test_init with sdr/ddr3/ddr4 references
2019-09-09 11:45:10 +02:00
bf5883cd43
rename sdram_init to init
2019-09-09 11:42:02 +02:00
23ccdc9c0c
modules: add DDR3 MT8KTF51264 SO-DIMM
2019-09-09 08:47:29 +02:00
d37a30e0d7
litedram_gen: add wishbone user port support
2019-09-03 23:47:08 +02:00
b6a0eff2d9
frontend/wishbone: split control/data paths (to avoid data muxes)
2019-09-03 12:44:07 +02:00
6497343fc0
frontend/wishbone: remove IDLE fsm state
2019-09-03 12:37:31 +02:00
00ecb871c4
gen: add separators
2019-09-03 12:37:05 +02:00
a782eb5aa8
test/test_examples: adapt for travis
2019-08-31 14:55:14 +02:00
f678efa02b
travis: add pyyaml
2019-08-29 12:13:05 +02:00
8861d8058a
Merge pull request #91 from sd-fritze/master
...
modules: Add support for Micron MT47H32M16 DDR2 RAM
2019-08-31 13:59:40 +02:00
fe2cc948dc
modules: Add support for Micron MT47H32M16 DDR2 RAM
2019-08-31 12:05:07 +02:00
a23b9e7877
core/refresher: set cmd.valid to 0 when sequencer done
2019-08-30 08:55:38 +02:00
12ddc135be
litedram/gen: add description and switch to argparse
2019-08-28 08:07:20 +02:00
2bdeda021b
move standalone core generation to litedram package and make it usable externally
...
When LiteDRAM is installed, standalone core can now be generated with "litedram_gen config.yml"
2019-08-28 07:19:30 +02:00
0dde125740
examples/litedram_gen: fix #!/usr/bin/env python3 location
2019-08-28 07:09:58 +02:00
602ff8be81
examples: switch to YAML config files
2019-08-28 07:08:10 +02:00
fb28f791c8
core/refresher: remove load/load_count on RefreshTimer (not used)
2019-08-16 08:52:36 +02:00
1c69f49760
core/controller: allow user provided Refresher
2019-08-16 08:39:08 +02:00
b64daba711
core/controller: add separators, ease readibility
2019-08-16 08:37:08 +02:00
338d18dba0
core/refresher: add capability to accumulate N refreshs and execute the N refreshs together
...
Being able to accumulate refreshs allow reducing the number of interruptions to the Controller from 1 every tREFI cycles to 1 every N*tREFI cycles.
2019-08-14 09:57:24 +02:00
818c4ca9db
core/refresher: another cleanup pass
2019-08-14 09:07:49 +02:00
Florent Kermarrec
Gabriel Somlo
Tim Ansell
Benjamin Herrenschmidt
gruetzkopf