f5e80bb010
Merge pull request #360 from Dolu1990/master
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litedram/address_mapping Add bank_byte_alignment
2024-08-27 08:59:36 +02:00
ee0972cd79
frontend/wishbone/LiteDRAMWishbone2Native: Fix assert.
2024-08-23 21:21:48 +02:00
15fe3d93d8
litedram/frontend/wishbone: Add initial LiteDRAMNative2Wishbone.
2024-08-22 09:12:34 +02:00
a194044f6f
litedram/frontend/wishbone: Switch to LiteXModule.
2024-08-22 08:51:37 +02:00
49688a52ce
litedram/address_mapping Add bank_byte_alignment
2024-07-18 17:51:23 +02:00
5ece090155
litedram/gen: Cleanup pass and switch to LiteXModule.
2024-06-19 10:41:50 +02:00
619598618c
Merge pull request #359 from VOGL-electronic/add_insignis_NDS36PT5
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modules: add Insignis NDS36PT5
2024-06-19 08:22:24 +02:00
2d5a66f644
modules: add Insignis NDS36PT5
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add Insignis NDS36PT5.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-06-13 12:09:48 +02:00
6bce3a2587
version: Bump to 2024.04.
2024-06-05 22:06:50 +02:00
7dacfaf684
Merge pull request #352 from maribu/litedram/phy/lpddrX/commands.py/fix-invalid-escape-sequence
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litedram/phy/lpddr*: fix use of invalid escape sequence
2024-03-25 19:06:08 +01:00
d6bf98790f
Merge pull request #354 from hansfbaier/downconvert-cleanup
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stable avalon frontend
2024-03-25 19:05:07 +01:00
d7344c04ad
frontend/avalon: Remove downconvert specific logic (no longer required with LiteDRAMNativePortConverter improvement).
2024-02-20 05:26:28 +07:00
ed1e569e29
frontend/adapter/LiteDRAMNativePortDownConverter: Do early ack of user cmd.
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To better decouple cmd/data paths in user logic.
2024-02-20 05:26:28 +07:00
5e7ba4ee71
frontend/avalon/SINGLE_WRITE: Remove writedata update and port.cmd.last (not useful).
2024-02-20 05:26:28 +07:00
ff9f75054e
frontend/avalon: Avoid byteenable clear (data) and clear cmd_ready_seen in START.
2024-02-20 05:26:28 +07:00
f1f5f637e7
frontend/avalon: Improve decoupling in START state.
2024-02-20 05:26:28 +07:00
b0503f1b00
frotend/avalon: Another simplifiation pass on start condition.
2024-02-20 05:26:28 +07:00
9950904cb5
frontend/avalon: Simplify start condition.
2024-02-20 05:26:28 +07:00
17527092db
frontend/avalon: First review pass to make codestyle more similar to other LiteX/LiteDRAM modules.
2024-02-20 05:26:28 +07:00
37e1f346e5
litedram/phy/lpddr*: fix use of invalid escape sequence
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This fixes multiple instances of:
litedram/phy/lpddr4/commands.py:209
litedram-2023.12/litedram/phy/lpddr4/commands.py:209: DeprecationWarning: invalid escape sequence '\d'
"BA(\d+)": lambda i: self.dfi.bank[i],
2024-01-11 09:46:43 +01:00
e9adaebf0d
setup.py: Fix/Revert classifiers.
2024-01-01 15:27:21 +01:00
8ed232f8dc
setup.py: Bump to 2023.12 to prepare release.
2023-12-25 15:33:14 +01:00
b55cd3d481
setup.py: Switch minimum Python version to 3.7 (To allow more than 255 arguents in functions).
2023-12-19 10:23:39 +01:00
6615941f0c
setup.py: Specify UTF-8 encoding for long_description/README.md.
2023-12-19 10:12:09 +01:00
3b4cb273ac
setup.py: Improve indentation.
2023-12-19 09:10:53 +01:00
e835544d95
CONTRIBUTORS: Update.
2023-11-10 10:40:24 +01:00
bacaae377a
README.md: Update.
2023-11-10 10:30:02 +01:00
16eb5a931c
Merge pull request #351 from trabucayre/gw5a_ddr3
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phy/gw5ddrphy: introducing GW5A DDR phy
2023-11-09 11:43:26 +01:00
da78fca00e
phy/gw5ddrphy: introducing GW5A DDR phy
2023-11-09 11:42:48 +01:00
e1434fa5c8
Merge pull request #350 from hansfbaier/master
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Add W9812G6JB SDRAM module
2023-11-09 08:21:57 +01:00
9cffe392ea
add W9812G6JB SDRAM module
2023-11-09 10:28:39 +07:00
4dec115023
setup.py: Update to 2023.08.
2023-09-18 08:40:57 +02:00
ed81c8cc86
phy/gw2ddrphy: Remove CHECKME now that working.
2023-08-29 16:48:10 +02:00
50fc6792e6
litedram/init: Cleanup supported memory generation.
2023-08-29 16:42:42 +02:00
6dadc11b21
phy/gw2ddrphy: fix cl/cwl latencies
2023-08-25 17:52:05 +02:00
afdf1aff43
phy: Remove useless WaitTimer imports.
2023-08-01 14:40:48 +02:00
39c0b0356c
bench/uartbone: Update with LiteX change.
2023-07-20 15:44:18 +02:00
b291032987
frontend/dma/LiteDRAMDMAReader: Simplify FIFO reservation and add last generation support.
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With this, last is now asserted on the last cycle of the DMA transfer, making behavior similar to WishboneDMAReader.
This is useful to create packets from DRAM data.
2023-07-11 16:40:52 +02:00
0ba7da9ee9
core/bankmachine: Switch back to Replicate since Constant does not support 0-width.
2023-07-07 12:38:56 +02:00
b148ade774
core/bankmachine: Minor cleanup on _AddressSlicer.col.
2023-07-07 09:56:15 +02:00
01355ff781
Merge pull request #313 from cklarhorst/master
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Add MT46H128M16 and change bankmaschine to not use A10 for col addresses.
2023-07-07 08:53:25 +02:00
6f53acae22
Merge pull request #343 from trabucayre/fix_gw2ddrphy_import
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phy/gw2ddrphy: migen.genlib -> litex.gen.genlib (fix commit 6297370e3c
2023-07-07 08:50:25 +02:00
17ade2a512
ci: Use same fixed verilator commit than litex.
2023-07-07 08:46:20 +02:00
b8c7582274
phy/gw2ddrphy: migen.genlib -> litex.gen.genlib (fix commit 6297370e3c)
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Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
2023-07-07 07:46:32 +02:00
6297370e3c
global: Switch to litex.gen.genlib.misc.
2023-07-06 22:06:16 +02:00
e446c06339
frontend/avalon: properly implement bursts ( #340 )
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frontend/avalon: properly implement bursts
2023-05-31 08:14:52 +02:00
83a29b190d
Add support for clam shell topology ( #332 )
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Add clam shell topology support.
2023-05-25 22:20:21 +02:00
d8c327b2b1
ci: Increase similarities with LiteX CI.
2023-05-23 16:41:59 +02:00
b452f09df6
frontend/avalon: Minor cosmetic fixes.
2023-05-23 14:57:36 +02:00
f1293eae1e
Avalon frontend for LiteDRAM ( #337 )
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Add initial Avalon MM frontend + tests.
2023-05-23 14:52:05 +02:00
enjoy-digital
Dolu1990
Fin Maaß
Marian Buschsieweke
Gwenhael Goavec-Merou
Hans Baier
Gwenhael Goavec-Merou
Chen