Jędrzej Boczar
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ff435fd26e
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test: add option to run benchmarks with alternating write/read
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2020-02-11 12:06:45 +01:00 |
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Jędrzej Boczar
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6093f2012e
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test: add run/ready signals to BIST modules
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2020-02-11 11:45:01 +01:00 |
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Jędrzej Boczar
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cf5939f09e
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test: use Memory instead of Case for custom access pattern
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2020-02-07 14:58:33 +01:00 |
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Jędrzej Boczar
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9148400ef5
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test: fix typo, add note about limitations
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2020-02-07 12:20:43 +01:00 |
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Jędrzej Boczar
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2825c080a9
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test: fix problem with plot labels overlapping for large number of benchmarks
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2020-02-07 09:52:31 +01:00 |
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Jędrzej Boczar
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77541c3670
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test: avoid instantiating LiteDRAMBenchmarkSoC to speed up summary generation
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2020-02-06 15:08:01 +01:00 |
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Jędrzej Boczar
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027034db49
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test: add option to run benchmarks as parallel jobs
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2020-02-06 15:07:55 +01:00 |
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Jędrzej Boczar
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62a5473ecd
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test: update script for generating benchmark configurations
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2020-02-06 13:35:34 +01:00 |
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Jędrzej Boczar
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8ba3cced60
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test: add new benchmark configuratiosns to example configuration file
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2020-02-05 18:58:49 +01:00 |
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Jędrzej Boczar
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1702e2ad7c
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test: update summary to work for all configurations (use pandas)
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2020-02-05 18:39:06 +01:00 |
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Jędrzej Boczar
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f9f86d507f
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test: update benchmark configuration to account for access pattern
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2020-02-05 12:54:33 +01:00 |
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Jędrzej Boczar
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7e0515c477
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test: fix problem with helper scripts being executed by `setup.py test`
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2020-02-04 16:37:26 +01:00 |
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Jędrzej Boczar
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fcd3d4ff6c
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test: helper scripts for generating benchmark configurations/access patterns
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2020-02-04 16:26:57 +01:00 |
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Jędrzej Boczar
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fcbcd4d3fe
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test: add option to benchmark predefined access patterns
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2020-02-04 16:26:57 +01:00 |
enjoy-digital
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4a3ad56146
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Merge pull request #129 from antmicro/8-16-bit-init
phy/model: add support for 8/16-bit wide SDR memory init
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2020-02-04 11:29:28 +01:00 |
Piotr Binkowski
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6fd8f2172f
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phy/model: add support for 8/16-bit wide SDR memory init
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2020-02-04 10:51:56 +01:00 |
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Florent Kermarrec
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586980a4e5
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frontend/dma: test and fix add_csr on DMAs
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2020-02-03 19:47:49 +01:00 |
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enjoy-digital
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c536330e36
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Merge pull request #127 from antmicro/jboc/benchmark
Add Write/Read latency measurement
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2020-02-03 19:04:48 +01:00 |
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Jędrzej Boczar
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bae046f143
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test: add read/write latency benchmarks
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2020-02-03 16:59:12 +01:00 |
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enjoy-digital
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9aa421e52a
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Merge pull request #125 from antmicro/fix-init
phy/model: fix case when not converting init data width
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2020-02-03 15:09:49 +01:00 |
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Piotr Binkowski
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4c86235048
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phy/model: fix case when not converting init data width
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2020-02-03 13:35:49 +01:00 |
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enjoy-digital
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a903c87872
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Merge pull request #124 from antmicro/l2-reverse
phy/model: cleanup the memory init code
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2020-02-03 12:55:02 +01:00 |
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Jędrzej Boczar
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a584923f1c
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test: use JSON instead of pickle for storing benchmarks cache
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2020-02-03 12:17:41 +01:00 |
|
Piotr Binkowski
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99227ad0d0
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phy/model: cleanup the memory init code
After adding support for l2_reverse flag in Cache/SoCSDRAM we can remove
code responsible for word order reversing and do a general cleanup
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2020-02-03 12:02:49 +01:00 |
|
Florent Kermarrec
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736723cc98
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test/run_benchmarks: change YAML config file argument
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2020-02-03 10:38:10 +01:00 |
|
Florent Kermarrec
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7e95ecc9a9
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test/run_benchmark: avoid Python 3.7+ dependency
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2020-02-03 10:37:10 +01:00 |
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enjoy-digital
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d8f3feb971
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Merge pull request #123 from antmicro/jboc/benchmark
Add plotting of benchmark results
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2020-02-03 10:35:09 +01:00 |
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Jędrzej Boczar
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811c73254b
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test: benchmark script exits with error on any checker error
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2020-01-31 15:16:37 +01:00 |
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Jędrzej Boczar
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1a517a308d
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test: cache benchmark results to be able to produce multiple summaries
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2020-01-31 14:39:41 +01:00 |
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Jędrzej Boczar
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a40817f3a8
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test: add plotting of benchmark results
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2020-01-31 14:39:41 +01:00 |
|
enjoy-digital
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5a90a8b0dd
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Merge pull request #117 from antmicro/init-fixes
phy/model: init fixes
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2020-01-31 12:46:43 +01:00 |
|
Piotr Binkowski
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8fa7a93e5c
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phy/model: add support for sdram init for other memory types/widths
Up until now init worked correctly only on 32-bit SDR modules,
with this it should work at least with 64-bit wide DDR3, 128-bit DDR2
and 512-bit SDRAM
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2020-01-31 11:14:32 +01:00 |
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enjoy-digital
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eacfbd8055
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Merge pull request #122 from antmicro/jboc/benchmark
Load benchmark configuration from YAML
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2020-01-30 16:08:30 +01:00 |
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Jędrzej Boczar
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f6973aa9d7
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test: load benchmark configurations from YAML file
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2020-01-30 15:39:29 +01:00 |
|
Florent Kermarrec
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090620c9d6
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frontend/dma: add optional CSR control
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2020-01-30 15:21:37 +01:00 |
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Jędrzej Boczar
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096de78c63
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test: fix `setup.py test` failing due to import error
because of relative import the script has to be run as:
python -m test.run_benchmarks
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2020-01-30 14:11:52 +01:00 |
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enjoy-digital
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e17e6e34d8
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Merge pull request #118 from antmicro/jboc/benchmark
Add a script for running LiteDRAM benchmarks
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2020-01-30 13:31:11 +01:00 |
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Jędrzej Boczar
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bb4f6106ee
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test: print benchmarks summary
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2020-01-30 10:50:08 +01:00 |
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Jędrzej Boczar
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e822e6be9f
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test: calculate benchmark bandwidth and efficiency
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2020-01-30 10:19:17 +01:00 |
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Jędrzej Boczar
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804a9b3727
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test: add script for running multiple benchmarks and parsing results
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2020-01-29 17:03:20 +01:00 |
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enjoy-digital
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a35a1f7790
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Merge pull request #116 from antmicro/jboc/benchmark
test: add command line arguments for BIST base/length/random
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2020-01-28 15:42:27 +01:00 |
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Jędrzej Boczar
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502e6c663c
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test: add command line arguments for BIST base/length/random
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2020-01-28 15:03:36 +01:00 |
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enjoy-digital
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72e65e697f
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Merge pull request #115 from antmicro/ddr4-model
phy/model: add burst_length value for ddr4 memories
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2020-01-28 14:48:00 +01:00 |
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Piotr Binkowski
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cd25106fc1
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phy/model: add burst_length value for ddr4 memories
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2020-01-28 14:23:35 +01:00 |
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enjoy-digital
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6b91c1fa86
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Merge pull request #111 from antmicro/write-latency
phy/model: simulate write latency
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2020-01-28 14:05:16 +01:00 |
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Piotr Binkowski
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f9d00f137b
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phy/model: simulate write latency
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2020-01-28 12:38:17 +01:00 |
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Florent Kermarrec
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586eb39b1d
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test: add initial benchmark test
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2020-01-28 12:07:22 +01:00 |
|
Florent Kermarrec
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e4f901f070
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phy/model: review/simplify initialization
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2020-01-27 21:29:08 +01:00 |
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enjoy-digital
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9c00255483
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Merge pull request #104 from antmicro/phy-model-init
phy/model: add support for initializing memory from file
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2020-01-27 20:54:51 +01:00 |
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Florent Kermarrec
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e5e4f528d4
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examples/versa_ecp5.yml: enable CPU (required for DDR3 calibration), update copyright
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2020-01-27 18:30:24 +01:00 |