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Author SHA1 Message Date
Florent Kermarrec
ccdb85bcb7 doc: add simple architecture diagram 2017-11-13 17:39:09 +01:00
Florent Kermarrec
edb51944d5 Merge branch 'master' of https://github.com/enjoy-digital/liteeth 2017-11-06 19:02:42 +01:00
Florent Kermarrec
a20ff49c90 example_designs/test: keep up to date with litescope 2017-11-06 19:01:51 +01:00
Florent Kermarrec
26c01a1627 core/mac/crc: fix crc_error generation 2017-11-01 23:23:02 +01:00
Florent Kermarrec
eaf4acc3f5 core/mac: apply misoc changes (72faa2c) 2017-11-01 21:11:08 +01:00
Florent Kermarrec
937c240727 test: fix test_model 2017-09-25 13:12:30 +02:00
enjoy-digital
48fb4647bd Merge pull request #6 from enjoy-digital/port-1234 
Adding TCP port 1234 to Etherbone dissector.
 2017-09-01 15:23:22 +02:00
Tim Ansell
00e6ded2e9 Adding TCP port 1234 to Etherbone dissector. 
LiteEth designs seem to commonly use TCP port 1234.
 2017-09-01 23:16:09 +10:00
Florent Kermarrec
c43fb269a7 frontend/etherbone: timing optimizations 2017-07-19 12:20:17 +02:00
Florent Kermarrec
042d3aee3e frontend/etherbone: fix cd="sys case 2017-07-15 22:10:48 +02:00
Florent Kermarrec
1127e3a615 core/udp: simplify LiteEthUDPCrossbar.get_port when used with cdc 2017-07-01 13:14:13 +02:00
Florent Kermarrec
b870d13d96 global: reset_less optimizations 2017-07-01 11:22:26 +02:00
Florent Kermarrec
34460cec47 core/udp: add cdc support (untested) 2017-06-30 11:01:44 +02:00
Florent Kermarrec
5bc6e879ae update litescope 2017-06-23 09:14:19 +02:00
Florent Kermarrec
ad9ecdbd5e use udp port 1234 for etherbone 2017-06-22 11:28:45 +02:00
Florent Kermarrec
e68e2ed73c frontend/etherbone: add description 2017-04-26 23:43:43 +02:00
Florent Kermarrec
f6d8ddbba0 update litex uart 2017-04-19 10:39:52 +02:00
Florent Kermarrec
62acb5df52 example_designs: update 2017-03-30 14:46:54 +02:00
Florent Kermarrec
42454a5448 frontend/etherbone: add wishbone slave support (allow extending wishbone bridge over ethernet between boards) 2017-03-30 14:46:30 +02:00
Florent Kermarrec
a067691222 README: update 2017-01-19 14:53:11 +01:00
Florent Kermarrec
c4856d1eb5 test: start converting to python unittest 2017-01-19 14:33:24 +01:00
Florent Kermarrec
e1da2df97d core/mac/sram: fix reception of frames larger than mtu 
-use 32bits length CSR (allow software to detect frames larger than mtu)
-drop remaining bytes larger than mtu
 2016-05-01 07:37:24 +02:00
Florent Kermarrec
072969ff58 common: fix eth_mtu (1530 bytes) 2016-05-01 07:09:37 +02:00
Florent Kermarrec
94290016d0 setup.py: fix version (0.1) 2016-04-29 14:32:05 +02:00
Florent Kermarrec
33e36dc4d7 use new Record.connect omit parameter (replace leave_out) 2016-04-21 08:03:31 +02:00
enjoy-digital
8590310783 Merge pull request #2 from mithro/master 
Adding a .gitignore file.
 2016-04-19 06:07:22 +02:00
Tim 'mithro' Ansell
2207cf3cc3 Adding a .gitignore file. 2016-04-19 13:02:12 +10:00
Florent Kermarrec
f55ce1aac6 core/mac: simplify/improve performance of LiteEthMACSRAMReader 
now read data from sram on every clock cycle, allow lower system clock frequency (tested with 50MHz system clock / 125MHz ethernet clock)
 2016-04-03 22:53:02 +02:00
Florent Kermarrec
c6875b7bff example_designs: use new litescope 2016-03-31 21:27:08 +02:00
Florent Kermarrec
e006223fee test: fix model_tb 2016-03-31 00:25:50 +02:00
Florent Kermarrec
de5410429b README: we are in 2016 2016-03-31 00:06:08 +02:00
Florent Kermarrec
a189b2c195 phy/s6rgmii: fix missing last signal 2016-03-29 16:53:37 +02:00
Florent Kermarrec
b394f2f45e test/mac_wishbone_tb: fix simulation 2016-03-25 12:26:02 +01:00
Florent Kermarrec
b7f3b3ef42 test: finish etherbone_tb (simulator limitation removed) 2016-03-23 09:48:02 +01:00
Florent Kermarrec
87924c84e6 test: finish mac_wishbone_tb (simulator limitation removed) 2016-03-23 09:47:47 +01:00
Florent Kermarrec
7ea1b5a22d test: use passive generators and some cleanup 2016-03-23 01:42:35 +01:00
Florent Kermarrec
e73f35c733 test: remove __init__.py and use setup.py develop 2016-03-22 10:34:28 +01:00
Florent Kermarrec
2f15f3748e test: use new simulator (still etherbone_tb and mac_wishbone_tb not working due to use of FullMemoryWE) 2016-03-21 19:59:29 +01:00
Florent Kermarrec
657ba4cb16 global: use valid/ready/last signals instead of stb/ack/eop (similar to AXI) 2016-03-16 21:36:07 +01:00
Florent Kermarrec
9cd7dc3088 global: use SyncFIFO instead of Buffer 2016-03-16 19:45:43 +01:00
Florent Kermarrec
aff07c6809 global: use new StrideConverter 2016-03-16 17:01:13 +01:00
Florent Kermarrec
51f56e79dd global: remove use of sop 2016-03-16 16:22:00 +01:00
Florent Kermarrec
1f46aaeb55 core/mac: remove frontend directory (too much directories) and some cleanup 2016-03-15 20:09:30 +01:00
Florent Kermarrec
c3e15e7f7b core/mac: use fifo_depth of 64 for all phys 2016-03-15 19:41:53 +01:00
Florent Kermarrec
32243934fb global: use stream.Endpoint instead of Sink/Source (deprecated) 2016-03-15 16:50:00 +01:00
Florent Kermarrec
9593e29756 global: use 192.168.1.100 (remote)/ 192.168.1.50 (local) IP addresses 2016-03-15 15:40:06 +01:00
Florent Kermarrec
b7efe0fd46 phy: remove pads_register parameter (does not save enough, priority to simplicity) 2016-03-15 15:33:36 +01:00
Florent Kermarrec
5583fe5543 phy/s6rgmii: RenameClockDomains --> ClockDomainsRenamer 2016-02-24 23:51:31 +01:00
Florent Kermarrec
1dae2b802c example_design/targets/core: cleanup 2016-02-10 10:50:38 +01:00
Florent Kermarrec
36399d65da example_designs/targets/core: add possibility to build udp cores (with hw udp/ip stack) 2016-02-10 10:29:23 +01:00