Commit Graph

578 Commits

Author SHA1 Message Date
Florent Kermarrec 022207c5c6 liteeth_gen: Use fixed CSR mapping to avoid moving base addresses with LiteX changes/simplifications. 2022-10-24 09:10:24 +02:00
Florent Kermarrec e9cdaa01a5 ci: Bump to ubuntu 20.04. 2022-10-14 18:17:35 +02:00
Florent Kermarrec 8fc5ed0ded CONTRIBUTORS: Update. 2022-09-07 10:20:11 +02:00
Florent Kermarrec 6cf7759c9b frontend/stream: Add packet support and remove send_level.
TX packets are now sent when we have a full packet of when the FIFO is full.
Last can always be asserted from user-side when packet needs to be immediately
transmitted, the behavior will then be similar to previous implementation.

Errors are now also reported on RX.
2022-07-29 14:58:25 +02:00
Florent Kermarrec 6d742e7999 phy/titaniumrgmii: Switch tx_ctl to IO primitive (similar to tx_data) and fix cd_eth_tx reset. 2022-07-08 12:16:09 +02:00
Florent Kermarrec c035ee2b63 liteeth/gen: Fix phy_tx/rx_delay format (floats). 2022-07-07 18:01:26 +02:00
Florent Kermarrec 8ad6e2521c phy: Add initial Titanium RGMII PHY (based on Trion's PHY). 2022-06-27 19:42:51 +02:00
Florent Kermarrec a319588843 liteeth/core: Expose IP broadcast capability. 2022-06-27 15:46:23 +02:00
Florent Kermarrec f192183255 liteeth/gen: Revert and fix missing Wishbone interface. 2022-06-27 15:35:37 +02:00
enjoy-digital 6930fb1cfb
Merge pull request #110 from Xiretza/gen-fix-rmii
gen: fix for RMII PHY
2022-06-27 15:31:17 +02:00
Xiretza a543ec757b gen: fix for RMII PHY
Without setting the ref clock domain to None, generation failed:

Traceback (most recent call last):
  File "/usr/lib/python3.10/site-packages/litex/gen/fhdl/verilog.py", line 535, in convert
    f.clock_domains[cd_name]
  File "/usr/lib/python3.10/site-packages/migen/fhdl/structure.py", line 741, in __getitem__
    raise KeyError(key)
KeyError: 'eth'

During handling of the above exception, another exception occurred:

Traceback (most recent call last):
  File "/usr/bin/liteeth_gen", line 33, in <module>
    sys.exit(load_entry_point('liteeth==0.0.0', 'console_scripts', 'liteeth_gen')())
  File "/usr/lib/python3.10/site-packages/liteeth/gen.py", line 389, in main
    builder.build(build_name="liteeth_core")
  File "/usr/lib/python3.10/site-packages/litex/soc/integration/builder.py", line 350, in build
    vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
  File "/usr/lib/python3.10/site-packages/litex/soc/integration/soc.py", line 1208, in build
    return self.platform.build(self, *args, **kwargs)
  File "/usr/lib/python3.10/site-packages/litex/build/xilinx/platform.py", line 73, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/usr/lib/python3.10/site-packages/litex/build/xilinx/vivado.py", line 349, in build
    v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
  File "/usr/lib/python3.10/site-packages/litex/build/xilinx/platform.py", line 64, in get_verilog
    return GenericPlatform.get_verilog(self, *args,
  File "/usr/lib/python3.10/site-packages/litex/build/generic_platform.py", line 423, in get_verilog
    return verilog.convert(fragment, platform=self, **kwargs)
  File "/usr/lib/python3.10/site-packages/litex/gen/fhdl/verilog.py", line 541, in convert
    raise Exception(msg)
Exception: Unresolved clock domain eth, availables:
- sys
- por
- eth_rx
- eth_tx
2022-05-25 17:13:39 +02:00
Florent Kermarrec b0e7243123 liteeth_gen: Add data_width support (For 32/8-bit datapath). 2022-05-16 13:38:05 +02:00
Florent Kermarrec e2c1b81cd3 CONTRIBUTORS: Update. 2022-05-02 13:45:04 +02:00
Florent Kermarrec 6d71adae2b bench: Use full imports. 2022-05-02 13:09:28 +02:00
Florent Kermarrec d10cda84b6 core/LiteEthIPCore/LiteEthUDPIPCore: Expose with_sys_datapath parameter. 2022-04-25 17:48:54 +02:00
Florent Kermarrec 28c8871624 core/LiteEthIPCore/LiteEthUDPIPCore: Improve code readability. 2022-04-25 17:33:32 +02:00
enjoy-digital 2f6ac9a216
Merge pull request #105 from yetifrisstlama/master
packet.py: fix typo in Packetizer
2022-04-25 16:37:10 +02:00
enjoy-digital 678995c3cb
Merge pull request #97 from david-sawatzke/dev/liteethudprxfix
core/udp: Add dw>8 support to LiteEthUDPRX
2022-04-25 16:36:10 +02:00
Florent Kermarrec d20f36a6ba core/icmp/LiteEthICMPEcho: Revert to PacketFIFO now that issue is understood.
edd98c23cb
2022-04-25 15:55:59 +02:00
Florent Kermarrec 9c0a9659c1 bench/butterstick: Add JTAGBone and Analyzer in MAC/ARP/IP/UDP/Etherbone control path. 2022-04-25 15:38:55 +02:00
Florent Kermarrec 2a4d387563 bench: Add gsd_butterstick. 2022-04-25 14:26:43 +02:00
Michael Betz 5e4dd913fc packet.py: fix typo in Packetizer
* in some cases, the delayed sink data was updated even though
    sink was not valid, leading to corrupted source data
  * this broke etherbone reads with DW=64
2022-04-19 01:15:10 +02:00
Florent Kermarrec bc9162d578 frontend/etherbone: Add assert on buffer_depth to prevent miss-configuration. 2022-04-08 09:27:52 +02:00
Florent Kermarrec 4cd0a99187 phy/1000basex: Add crg_reset CSR for consistency with other PHYs. 2022-03-23 08:44:52 +01:00
Florent Kermarrec 9ab4419382 frontend/etherbone: Replace is by ==. (Reported by python3.8). 2022-03-16 16:46:37 +01:00
enjoy-digital 2eba4e6bbf
Merge pull request #102 from sergachev/master
phy/a7_1000basex: expose rx/tx polarity controls
2022-02-21 08:54:21 +01:00
Ilia Sergachev 4fdf0ea20e phy/a7_1000basex: expose rx/tx polarity controls 2022-02-20 18:25:23 +01:00
Florent Kermarrec d1d2ad4584 frontend/stream: Add with_broadcast parameter to allow broadcast reception (Enabled by default). 2022-02-16 14:13:54 +01:00
Florent Kermarrec dc96269c8f core/ip/tx: Add broadcast capability. 2022-02-16 14:12:46 +01:00
Florent Kermarrec aff1916a03 core/ip: Add with_broadcast parameter and set it to True by default (Allow IP broadcast reception). 2022-02-16 11:51:57 +01:00
David Sawatzke 72b1a1f91e core/udp: Add dw>8 support to LiteEthUDPRX
Pass through last_be or create a new one based on the length if needed

Initialize count at dw//8 and don't subtract source_length since it
could lead to underflow for very short packets. In case source.length is
not dw aligned, count will not be equal, so adjust comparison for that.

Crib last_be Case lookup from mac/sram.py
2022-02-04 17:16:20 +01:00
Florent Kermarrec b903b7257b frontend/stream: Switch FIFOs to buffered. 2022-02-03 15:58:06 +01:00
Florent Kermarrec 35b475727c frontend/stream/LiteEthStream2UDPTX: Fix length computation (depends on data_width). 2022-02-03 15:17:07 +01:00
Florent Kermarrec ba20fc7b71 liteeth_gen/udp: Improve flexibility and add support for multiple UDP virtual channels. 2022-01-28 10:11:45 +01:00
Florent Kermarrec 680806997d liteeth_gen/udp: Directly integrate UDPStreamer to simplify use and just expose a LiteX-Stream/AXI-ST interface. 2022-01-26 11:18:48 +01:00
Florent Kermarrec 2beec096b4 liteeth_gen: Move MAC/IP address configuration to Config section and add dynamic UDP port support. 2022-01-26 10:53:23 +01:00
Florent Kermarrec e0124748aa crossbar/LiteEthCrossbar: Allow dispatch_param to be a Signal to allow dynamic configuration from design. 2022-01-26 10:51:07 +01:00
Florent Kermarrec e340428384 liteeth_gen: Add configurable/dynamic MAC/IP address support. 2022-01-26 10:21:47 +01:00
Florent Kermarrec f264c9d5d5 liteeth_gen: Add toolchain support/parameter.
LiteX code specialization/generation can be different between toolchain (For the same vendor).
Add parameter to configure it from the .yml file.
2022-01-26 09:57:43 +01:00
Florent Kermarrec b38ca8d7c0 stream/LiteEthUDPStreamer: Add cd parameter. 2022-01-25 19:36:50 +01:00
Florent Kermarrec 14edaaeec2 frontend/stream: Add data_width support. 2022-01-14 18:38:21 +01:00
Florent Kermarrec 6a6bc28869 frontend/stream: Set sink.ready when udp_port or ip_address are invalid. 2022-01-14 18:02:53 +01:00
Florent Kermarrec 8faba46517 frontend/stream: Make ip_address filtering optional on LiteEthUDP2StreamRX. 2022-01-14 17:56:17 +01:00
enjoy-digital c3e3dee0e9
Merge pull request #100 from fjullien/fix_trionrgmii
phy: trionrgmii: add 'properties' to GPIO
2022-01-13 14:31:39 +01:00
Franck Jullien 31af9cabc2 phy: trionrgmii: add 'properties' to GPIO 2022-01-12 16:35:46 +01:00
Florent Kermarrec 561677634a Bump year. 2022-01-05 09:02:37 +01:00
enjoy-digital b317dc3558
Merge pull request #98 from yetifrisstlama/icmp
icmp: only send a ping reply to type 8 (ping request) packets
2022-01-05 08:35:20 +01:00
Michael Betz bc073a5d2c icmp.py: take icmp type field into account
* only send a ping reply to type 8 (ping request) packets
  * otherwise liteeth would send a ping reply to
    `destination unreachable` packets too, which is not wanted
2021-12-28 00:10:28 +01:00
Florent Kermarrec a8d9c5ef6a core/icmp: Revert to SyncFIFO for now until PacketFIFO regression is investigated. 2021-12-27 11:00:22 +01:00
enjoy-digital 7acb2a8c1c
Merge pull request #96 from lschuermann/dev/compliant-xgmii-fixup
phy/xgmii: remove vcd dump in test, fix comment
2021-11-21 21:19:17 +01:00