e73f35c733
test: remove __init__.py and use setup.py develop
2016-03-22 10:34:28 +01:00
2f15f3748e
test: use new simulator (still etherbone_tb and mac_wishbone_tb not working due to use of FullMemoryWE)
2016-03-21 19:59:29 +01:00
657ba4cb16
global: use valid/ready/last signals instead of stb/ack/eop (similar to AXI)
2016-03-16 21:36:07 +01:00
51f56e79dd
global: remove use of sop
2016-03-16 16:22:00 +01:00
32243934fb
global: use stream.Endpoint instead of Sink/Source (deprecated)
2016-03-15 16:50:00 +01:00
d38612db0c
remove use of Record.connect
2015-12-27 12:26:01 +01:00
f1725d5fd1
ethetbone software is now integrated in LiteX
2015-11-17 12:04:04 +01:00
e7caf8acfb
use stream_packet and stream_sim from litex
2015-11-14 00:42:33 +01:00
d84d610104
simulations working with litex and vpi
2015-11-13 15:11:57 +01:00
7b9dc92b0b
for now use our fork of migen
2015-11-13 14:48:53 +01:00
886108eee9
test: for now revert all simulation (we'll switch when missing feature of new simulator will be implemted)
2015-11-13 14:47:57 +01:00
57b70c640c
start adapting simulations to new migen (still some issues with Migen simulator)
...
Simulator issues:
- MultiReg not simulated correctly (I've used direct instantiation of MultiRegImpl to get simulation working)
- MemoryArray with granularity != 1 raise NotImplementedError
2015-11-13 13:46:05 +01:00
e33937f089
move etherbone packets and record description to software
2015-10-13 21:36:37 +02:00
b4c3223a24
update litescope and build Devel targets in test
2015-09-27 19:17:07 +02:00
d786380cd2
fix simulations (adapt to new organization) and and all target in Makefile to for regression testing
2015-09-12 20:53:14 +02:00
1d9ea484e2
test/Makefile: add example_designs to test regression on example_designs (only generate hdl)
2015-09-12 16:28:09 +02:00
306162096b
fix imports
2015-09-08 09:55:43 +02:00
20fc519410
init repo
2015-09-07 13:29:34 +02:00
Florent Kermarrec