litex-boards/litex_boards/targets/camlink_4k.py

133 lines
5.1 KiB
Python
Raw Normal View History

2020-01-08 03:56:37 -05:00
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
2020-01-08 03:56:37 -05:00
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import camlink_4k
from litex.build.lattice.trellis import trellis_args, trellis_argdict
2020-01-08 03:56:37 -05:00
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
2020-01-08 03:56:37 -05:00
from litex.soc.integration.builder import *
2020-05-09 06:27:07 -04:00
from litex.soc.cores.led import LedChaser
2020-01-08 03:56:37 -05:00
from litedram.modules import MT41K64M16
from litedram.phy import ECP5DDRPHY
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
2020-01-08 03:56:37 -05:00
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain()
2020-01-08 03:56:37 -05:00
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_i = ClockDomain()
2020-01-08 03:56:37 -05:00
# # #
self.stop = Signal()
# clk / rst
clk27 = platform.request("clk27")
# power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(ClockSignal())
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# pll
self.submodules.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(~por_done | self.rst)
2020-01-08 03:56:37 -05:00
pll.register_clkin(clk27, 27e6)
pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
pll.create_clkout(self.cd_init, 27e6)
self.specials += [
Instance("ECLKSYNCB",
i_ECLKI = self.cd_sys2x_i.clk,
i_STOP = self.stop,
o_ECLKO = self.cd_sys2x.clk),
Instance("CLKDIVF",
p_DIV = "2.0",
i_ALIGNWD = 0,
i_CLKI = self.cd_sys2x.clk,
i_RST = self.cd_sys2x.rst,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked)
2020-01-08 03:56:37 -05:00
]
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, toolchain="trellis", with_led_chaser=True, **kwargs):
2020-01-08 03:56:37 -05:00
platform = camlink_4k.Platform(toolchain=toolchain)
sys_clk_freq = int(81e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Cam Link 4K",
**kwargs)
2020-01-08 03:56:37 -05:00
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K64M16(sys_clk_freq, "1:2"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
2020-01-08 03:56:37 -05:00
# Leds -------------------------------------------------------------------------------------
# Disable leds when serial is used.
if platform.lookup_request("serial", loose=True) is None and with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
2020-01-08 03:56:37 -05:00
# Build --------------------------------------------------------------------------------------------
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Cam Link 4K")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=81e6, help="System clock frequency.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
2020-01-08 03:56:37 -05:00
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
2020-01-08 03:56:37 -05:00
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
toolchain = args.toolchain,
**soc_core_argdict(args)
)
2020-01-08 03:56:37 -05:00
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram", ext=".svf")) # FIXME
2020-01-08 03:56:37 -05:00
if __name__ == "__main__":
main()