litex-boards/litex_boards/targets/arty.py

163 lines
6.3 KiB
Python
Raw Normal View History

2019-06-10 11:09:51 -04:00
#!/usr/bin/env python3
2019-07-12 13:19:01 -04:00
# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
2019-06-10 11:09:51 -04:00
import argparse
from migen import *
from litex_boards.platforms import arty
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
2019-06-10 11:09:51 -04:00
from litex.soc.cores.clock import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litedram.modules import MT41K128M16
from litedram.phy import s7ddrphy
from liteeth.phy.mii import LiteEthPHYMII
2019-07-12 13:19:01 -04:00
from liteeth.mac import LiteEthMAC
2020-01-16 04:28:09 -05:00
from liteeth.core import LiteEthUDPIPCore
from liteeth.frontend.etherbone import LiteEthEtherbone
2019-06-10 11:09:51 -04:00
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
2019-06-10 11:09:51 -04:00
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_eth = ClockDomain()
2019-06-10 11:09:51 -04:00
# # #
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk100"), 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
2019-06-10 11:09:51 -04:00
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6)
pll.create_clkout(self.cd_eth, 25e6)
2019-06-10 11:09:51 -04:00
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
2019-06-10 11:09:51 -04:00
platform = arty.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
2019-06-10 11:09:51 -04:00
# CRG --------------------------------------------------------------------------------------
2019-06-10 11:09:51 -04:00
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT41K128M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings = sdram_module.geom_settings,
timing_settings = sdram_module.timing_settings)
2019-06-10 11:09:51 -04:00
# EthernetSoC --------------------------------------------------------------------------------------
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0xb0000000,
2019-06-10 11:09:51 -04:00
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
2019-06-10 11:09:51 -04:00
2020-01-16 04:28:09 -05:00
# Ethernet ---------------------------------------------------------------------------------
# phy
self.submodules.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
2019-06-10 11:09:51 -04:00
self.add_csr("ethphy")
2020-01-16 04:28:09 -05:00
# mac
self.submodules.ethmac = LiteEthMAC(
phy = self.ethphy,
dw = 32,
interface = "wishbone",
endianness = self.cpu.endianness)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
2019-06-10 11:09:51 -04:00
self.add_csr("ethmac")
self.add_interrupt("ethmac")
2020-01-16 04:28:09 -05:00
# timing constraints
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/25e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/25e6)
2019-06-10 11:09:51 -04:00
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
2020-01-16 04:28:09 -05:00
# EtherboneSoC -------------------------------------------------------------------------------------
class EtherboneSoC(BaseSoC):
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
# Ethernet ---------------------------------------------------------------------------------
# phy
self.submodules.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
# core
self.submodules.ethcore = LiteEthUDPIPCore(
phy = self.ethphy,
mac_address = 0x10e2d5000000,
ip_address = "192.168.1.50",
clk_freq = self.clk_freq)
# etherbone
self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234)
self.add_wb_master(self.etherbone.wishbone.bus)
# timing constraints
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/25e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/25e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
2019-06-10 11:09:51 -04:00
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty")
builder_args(parser)
soc_sdram_args(parser)
vivado_build_args(parser)
2020-01-16 04:28:09 -05:00
parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support")
parser.add_argument("--with-etherbone", action="store_true", help="enable Etherbone support")
2019-06-10 11:09:51 -04:00
args = parser.parse_args()
2020-01-16 04:28:09 -05:00
assert not (args.with_ethernet and args.with_etherbone)
cls = BaseSoC
if args.with_ethernet:
cls = EthernetSoC
if args.with_etherbone:
cls = EtherboneSoC
2019-06-10 11:09:51 -04:00
soc = cls(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args))
2019-06-10 11:09:51 -04:00
if __name__ == "__main__":
main()