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__init__.py
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Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
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2020-02-03 09:36:30 +01:00 |
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ac701.py
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targets: avoid direct use of mem_decoder.
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2020-02-11 21:59:42 +01:00 |
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aller.py
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Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
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2020-02-03 09:36:30 +01:00 |
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arty.py
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platforms/targets: keep in sync with LiteX
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2020-02-27 11:06:53 +01:00 |
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c10lprefkit.py
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targets: avoid direct use of mem_decoder.
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2020-02-11 21:59:42 +01:00 |
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camlink_4k.py
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targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.
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2020-03-05 10:57:59 +01:00 |
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colorlight_5a_75b.py
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targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets).
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2020-02-28 09:46:54 +01:00 |
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de0nano.py
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Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
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2020-02-03 09:36:30 +01:00 |
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de1soc.py
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Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
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2020-02-03 09:36:30 +01:00 |
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de2_115.py
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Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
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2020-02-03 09:36:30 +01:00 |
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de10lite.py
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targets: avoid direct use of mem_decoder.
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2020-02-11 21:59:42 +01:00 |
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de10nano.py
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de10nano/MiSTer: rename SPI SD CARD pins to spisdcard and remove SPI SD Card integration from target.
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2020-03-19 11:09:48 +01:00 |
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ecp5_evn.py
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targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.
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2020-03-05 10:57:59 +01:00 |
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fomu.py
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Changed wrong imports for fomu board.
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2020-02-12 12:40:07 +01:00 |
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genesys2.py
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Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
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2020-02-03 09:36:30 +01:00 |
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hadbadge.py
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targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.
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2020-03-05 10:57:59 +01:00 |
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icebreaker.py
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targets/icebreaker: use simplified version closer to the others targets.
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2020-03-13 09:43:43 +01:00 |
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kc705.py
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targets/kc705: use DDRPHY_CMD_DELAY to center write leveling.
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2020-02-27 12:58:52 +01:00 |
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kcu105.py
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targets/Ultrascale(+): simplify CRG using USIDELAYCTRL.
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2020-03-10 16:55:22 +01:00 |
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kx2.py
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Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
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2020-02-03 09:36:30 +01:00 |
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linsn_rv901t.py
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targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
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2020-02-11 17:45:35 +01:00 |
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mercury_xu5.py
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targets/Ultrascale+: use 500MHz IDELAYCTRL reference clock.
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2020-03-10 16:58:30 +01:00 |
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mimas_a7.py
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targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
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2020-02-11 17:45:35 +01:00 |
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minispartan6.py
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Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
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2020-02-03 09:36:30 +01:00 |
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nereid.py
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Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
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2020-02-03 09:36:30 +01:00 |
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netv2.py
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targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
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2020-02-11 17:45:35 +01:00 |
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nexys4ddr.py
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targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
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2020-02-11 17:45:35 +01:00 |
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nexys_video.py
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Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
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2020-02-03 09:36:30 +01:00 |
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orangecrab.py
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targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.
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2020-03-05 10:57:59 +01:00 |
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pipistrello.py
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Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
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2020-02-03 09:36:30 +01:00 |
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simple.py
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targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
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2020-02-11 17:45:35 +01:00 |
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tagus.py
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Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
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2020-02-03 09:36:30 +01:00 |
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trellisboard.py
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targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.
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2020-03-05 10:57:59 +01:00 |
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ulx3s.py
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targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets).
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2020-02-28 09:46:54 +01:00 |
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vc707.py
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vc707: fix copyrights (Michael Betz is the initial author)
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2020-02-28 08:39:52 +01:00 |
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vcu118.py
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targets/Ultrascale+: use 500MHz IDELAYCTRL reference clock.
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2020-03-10 16:58:30 +01:00 |
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versa_ecp5.py
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targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.
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2020-03-05 10:57:59 +01:00 |
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zcu104.py
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targets/Ultrascale(+): simplify CRG using USIDELAYCTRL.
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2020-03-10 16:55:22 +01:00 |
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