litex-boards/litex_boards/targets/terasic_de2_115.py

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#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen import LiteXModule
from litex.build.io import DDROutput
from litex_boards.platforms import terasic_de2_115
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from litex.soc.cores.clock import CycloneIVPLL
from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
from litedram.modules import IS42S16320
from litedram.phy import GENSDRPHY
# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.cd_sys = ClockDomain()
self.cd_sys_ps = ClockDomain()
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# # #
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# Clk / Rst
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clk50 = platform.request("clk50")
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# PLL
self.pll = pll = CycloneIVPLL(speedgrade="-7")
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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# SDRAM clock
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=50e6, **kwargs):
platform = terasic_de2_115.Platform()
# CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on DE2-115", **kwargs)
# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = IS42S16320(self.clk_freq, "1:1"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
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# Build --------------------------------------------------------------------------------------------
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def main():
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=terasic_de2_115.Platform, description="LiteX SoC on DE2-115.")
parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
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args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = args.sys_clk_freq,
**parser.soc_argdict
)
builder = Builder(soc, **parser.builder_argdict)
if args.build:
builder.build(**parser.toolchain_argdict)
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if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
main()