2020-01-25 06:00:57 -05:00
|
|
|
#!/usr/bin/env python3
|
|
|
|
|
2020-08-23 09:00:17 -04:00
|
|
|
#
|
|
|
|
# This file is part of LiteX-Boards.
|
|
|
|
#
|
|
|
|
# Copyright (c) 2020 Paul Sajna <sajattack@gmail.com>
|
|
|
|
# SPDX-License-Identifier: BSD-2-Clause
|
2020-01-25 06:00:57 -05:00
|
|
|
|
|
|
|
from migen import *
|
|
|
|
from migen.genlib.resetsync import AsyncResetSynchronizer
|
|
|
|
|
2020-04-10 05:46:23 -04:00
|
|
|
from litex.build.io import DDROutput
|
|
|
|
|
2022-05-02 06:42:04 -04:00
|
|
|
from litex_boards.platforms import terasic_de10nano
|
2020-01-25 06:00:57 -05:00
|
|
|
|
2020-04-08 02:11:04 -04:00
|
|
|
from litex.soc.cores.clock import CycloneVPLL
|
2020-06-11 13:54:55 -04:00
|
|
|
from litex.soc.integration.soc import SoCRegion
|
2020-01-25 06:00:57 -05:00
|
|
|
from litex.soc.integration.soc_core import *
|
|
|
|
from litex.soc.integration.builder import *
|
2021-03-03 12:05:24 -05:00
|
|
|
from litex.soc.cores.video import VideoVGAPHY
|
2020-05-08 16:16:13 -04:00
|
|
|
from litex.soc.cores.led import LedChaser
|
2020-01-25 06:00:57 -05:00
|
|
|
|
2020-06-11 13:54:55 -04:00
|
|
|
from litedram.modules import AS4C32M16
|
2020-07-23 09:41:35 -04:00
|
|
|
from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
|
2020-01-25 06:00:57 -05:00
|
|
|
|
|
|
|
# CRG ----------------------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
class _CRG(Module):
|
2020-07-24 10:11:57 -04:00
|
|
|
def __init__(self, platform, sys_clk_freq, with_sdram=False, sdram_rate="1:1"):
|
2020-11-04 05:09:30 -05:00
|
|
|
self.rst = Signal()
|
2020-01-25 06:00:57 -05:00
|
|
|
self.clock_domains.cd_sys = ClockDomain()
|
2020-07-24 10:11:57 -04:00
|
|
|
if sdram_rate == "1:2":
|
|
|
|
self.clock_domains.cd_sys2x = ClockDomain()
|
2022-04-01 05:30:38 -04:00
|
|
|
self.clock_domains.cd_sys2x_ps = ClockDomain()
|
2020-07-23 09:41:35 -04:00
|
|
|
else:
|
2022-04-01 05:30:38 -04:00
|
|
|
self.clock_domains.cd_sys_ps = ClockDomain()
|
|
|
|
self.clock_domains.cd_vga = ClockDomain()
|
2020-07-24 10:11:57 -04:00
|
|
|
|
2020-01-25 06:00:57 -05:00
|
|
|
# # #
|
|
|
|
|
|
|
|
# Clk / Rst
|
|
|
|
clk50 = platform.request("clk50")
|
|
|
|
|
|
|
|
# PLL
|
2020-04-08 02:11:04 -04:00
|
|
|
self.submodules.pll = pll = CycloneVPLL(speedgrade="-I7")
|
2020-11-04 05:09:30 -05:00
|
|
|
self.comb += pll.reset.eq(self.rst)
|
2020-04-08 02:11:04 -04:00
|
|
|
pll.register_clkin(clk50, 50e6)
|
|
|
|
pll.create_clkout(self.cd_sys, sys_clk_freq)
|
2020-07-24 10:11:57 -04:00
|
|
|
if sdram_rate == "1:2":
|
|
|
|
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
|
2020-07-23 09:41:35 -04:00
|
|
|
pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90)
|
|
|
|
else:
|
|
|
|
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
|
2021-03-03 12:05:24 -05:00
|
|
|
pll.create_clkout(self.cd_vga, 40e6)
|
2020-06-11 13:54:55 -04:00
|
|
|
|
2020-04-10 05:46:23 -04:00
|
|
|
# SDRAM clock
|
2020-01-31 03:29:02 -05:00
|
|
|
if with_sdram:
|
2020-07-24 10:11:57 -04:00
|
|
|
sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
|
2020-07-23 09:41:35 -04:00
|
|
|
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
|
2020-01-25 06:00:57 -05:00
|
|
|
|
|
|
|
# BaseSoC ------------------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
class BaseSoC(SoCCore):
|
2021-07-06 17:39:37 -04:00
|
|
|
def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, with_mister_sdram=True,
|
|
|
|
with_mister_video_terminal=False, sdram_rate="1:1", **kwargs):
|
2022-05-02 06:42:04 -04:00
|
|
|
platform = terasic_de10nano.Platform()
|
2020-01-29 16:59:57 -05:00
|
|
|
|
|
|
|
# CRG --------------------------------------------------------------------------------------
|
2020-07-24 10:11:57 -04:00
|
|
|
self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=with_mister_sdram, sdram_rate=sdram_rate)
|
2020-01-29 16:59:57 -05:00
|
|
|
|
2022-04-21 06:17:26 -04:00
|
|
|
# SoCCore ----------------------------------------------------------------------------------
|
|
|
|
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on DE10-Nano", **kwargs)
|
|
|
|
|
2020-01-29 16:59:57 -05:00
|
|
|
# SDR SDRAM --------------------------------------------------------------------------------
|
2020-06-11 13:54:55 -04:00
|
|
|
if with_mister_sdram and not self.integrated_main_ram_size:
|
2020-07-24 10:11:57 -04:00
|
|
|
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
|
2021-01-04 05:38:07 -05:00
|
|
|
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
|
2020-03-21 07:43:39 -04:00
|
|
|
self.add_sdram("sdram",
|
2021-03-29 09:28:04 -04:00
|
|
|
phy = self.sdrphy,
|
|
|
|
module = AS4C32M16(sys_clk_freq, sdram_rate),
|
|
|
|
l2_cache_size = kwargs.get("l2_size", 8192)
|
2020-03-21 07:43:39 -04:00
|
|
|
)
|
2020-01-29 16:59:57 -05:00
|
|
|
|
2021-03-03 12:05:24 -05:00
|
|
|
# Video Terminal ---------------------------------------------------------------------------
|
|
|
|
if with_mister_video_terminal:
|
|
|
|
self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
|
|
|
|
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
|
2020-06-11 13:54:55 -04:00
|
|
|
|
|
|
|
# Leds -------------------------------------------------------------------------------------
|
2021-07-06 17:39:37 -04:00
|
|
|
if with_led_chaser:
|
|
|
|
self.submodules.leds = LedChaser(
|
|
|
|
pads = platform.request_all("user_led"),
|
|
|
|
sys_clk_freq = sys_clk_freq)
|
2020-06-08 06:05:58 -04:00
|
|
|
|
2020-01-25 06:00:57 -05:00
|
|
|
# Build --------------------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
def main():
|
2022-03-21 11:59:40 -04:00
|
|
|
from litex.soc.integration.soc import LiteXSoCArgumentParser
|
|
|
|
parser = LiteXSoCArgumentParser(description="LiteX SoC on DE10-Nano")
|
2022-03-21 13:30:10 -04:00
|
|
|
target_group = parser.add_argument_group(title="Target options")
|
2022-05-06 09:14:32 -04:00
|
|
|
target_group.add_argument("--build", action="store_true", help="Build design.")
|
2022-03-21 13:30:10 -04:00
|
|
|
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
|
|
|
|
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
|
|
|
|
target_group.add_argument("--with-mister-sdram", action="store_true", help="Enable SDRAM with MiSTer expansion board.")
|
|
|
|
target_group.add_argument("--with-mister-video-terminal", action="store_true", help="Enable Video Terminal with Mister expansion board.")
|
|
|
|
target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
|
2020-11-12 05:46:00 -05:00
|
|
|
builder_args(parser)
|
2021-03-24 10:01:23 -04:00
|
|
|
soc_core_args(parser)
|
2020-12-14 07:26:29 -05:00
|
|
|
args = parser.parse_args()
|
2020-11-12 12:07:28 -05:00
|
|
|
|
2020-06-11 13:54:55 -04:00
|
|
|
soc = BaseSoC(
|
2021-03-03 12:05:24 -05:00
|
|
|
sys_clk_freq = int(float(args.sys_clk_freq)),
|
|
|
|
with_mister_sdram = args.with_mister_sdram,
|
|
|
|
with_mister_video_terminal = args.with_mister_video_terminal,
|
|
|
|
sdram_rate = args.sdram_rate,
|
2021-03-24 10:01:23 -04:00
|
|
|
**soc_core_argdict(args)
|
2020-11-12 12:07:28 -05:00
|
|
|
)
|
2020-01-25 06:00:57 -05:00
|
|
|
builder = Builder(soc, **builder_argdict(args))
|
2022-05-06 09:14:32 -04:00
|
|
|
if args.build:
|
|
|
|
builder.build()
|
2020-01-25 06:00:57 -05:00
|
|
|
|
2020-05-05 09:11:38 -04:00
|
|
|
if args.load:
|
|
|
|
prog = soc.platform.create_programmer()
|
2022-03-17 04:21:05 -04:00
|
|
|
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
|
2020-01-25 06:00:57 -05:00
|
|
|
|
|
|
|
if __name__ == "__main__":
|
|
|
|
main()
|