litex-boards/litex_boards/targets/terasic_de1soc.py

98 lines
3.4 KiB
Python
Raw Normal View History

2019-06-10 11:09:51 -04:00
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
# SPDX-License-Identifier: BSD-2-Clause
2019-06-10 11:09:51 -04:00
from migen import *
2020-01-09 13:46:39 -05:00
from migen.genlib.resetsync import AsyncResetSynchronizer
2019-06-10 11:09:51 -04:00
from litex.gen import LiteXModule
from litex.build.io import DDROutput
from litex_boards.platforms import terasic_de1soc
2019-06-10 11:09:51 -04:00
from litex.soc.cores.clock import CycloneVPLL
from litex.soc.integration.soc_core import *
2019-06-10 11:09:51 -04:00
from litex.soc.integration.builder import *
2021-12-05 10:42:34 -05:00
from litex.soc.cores.led import LedChaser
2019-06-10 11:09:51 -04:00
from litedram.modules import IS42S16320
from litedram.phy import GENSDRPHY
# CRG ----------------------------------------------------------------------------------------------
2019-06-10 11:09:51 -04:00
class _CRG(LiteXModule):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.cd_sys = ClockDomain()
self.cd_sys_ps = ClockDomain()
2019-06-10 11:09:51 -04:00
# # #
2020-01-09 13:46:39 -05:00
# Clk / Rst
2019-06-10 11:09:51 -04:00
clk50 = platform.request("clk50")
2020-01-09 13:46:39 -05:00
# PLL
self.pll = pll = CycloneVPLL(speedgrade="-C6")
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
2020-01-09 13:46:39 -05:00
# SDRAM clock
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
2019-06-10 11:09:51 -04:00
# BaseSoC ------------------------------------------------------------------------------------------
2019-06-10 11:09:51 -04:00
class BaseSoC(SoCCore):
2021-12-05 10:42:34 -05:00
def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, **kwargs):
platform = terasic_de1soc.Platform()
# CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq)
2019-06-10 11:09:51 -04:00
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on DE1-SoC", **kwargs)
# SDR SDRAM --------------------------------------------------------------------------------
2019-06-10 11:09:51 -04:00
if not self.integrated_main_ram_size:
self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = IS42S16320(sys_clk_freq, "1:1"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
2019-06-10 11:09:51 -04:00
2021-12-05 10:42:34 -05:00
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.leds = LedChaser(
2021-12-05 10:42:34 -05:00
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
# Build --------------------------------------------------------------------------------------------
2019-06-10 11:09:51 -04:00
def main():
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=terasic_de1soc.Platform, description="LiteX SoC on DE1-SoC")
parser.add_target_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
2019-06-10 11:09:51 -04:00
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
**parser.soc_core_argdict
)
builder = Builder(soc, **parser.builder_argdict)
if args.build:
builder.build(**parser.toolchain_argdict)
2019-06-10 11:09:51 -04:00
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
2019-06-10 11:09:51 -04:00
if __name__ == "__main__":
main()