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913 Commits 9 Branches 14 Tags 11 MiB
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913 Commits

Author SHA1 Message Date
Sergiu Mosanu 7a738245af fix bitstream problem 2021-01-14 21:53:25 -05:00
Sergiu Mosanu 5a73eb0b6d initiate target and platform for alveo_u280 board 2021-01-14 18:35:43 -05:00
Florent Kermarrec 6a5f2f59a6 targets/orangecrab: use new ECP5DDRPHY's cmd_delay to add extra delay on DDR3's Clock/Commands. 
This fixes https://github.com/enjoy-digital/litedram/issues/130 and has been tested
at 48/64/96MHz on MT41K64M16 and MT41K512M16 variants.

Also remove un-needed cd_sys2x_eb.
 2021-01-12 18:57:22 +01:00
Florent Kermarrec 9ff90eb9fe targets/c10lprefkit: fix default sys-clk-freq. 2021-01-12 16:15:52 +01:00
Florent Kermarrec 0a7443d273 targets/orangecrab: make usr_btn optional to fix compilation with revision 0.1. 2021-01-08 19:30:37 +01:00
Florent Kermarrec ae5494d7b6 orangecrab: defaults to USB-ACM UART. 2021-01-08 19:01:41 +01:00
Florent Kermarrec c6e75122d9 sds1104xe: defaults to Crossover UART. 2021-01-08 19:00:41 +01:00
Florent Kermarrec ab72f69937 targets/ac701: rename --ethernet-phy to --eth-phy for consistency with others targets. 2021-01-08 18:50:01 +01:00
Hans Baier 0ee62dd681 add etherbone ip address option for relevant boards 2021-01-08 18:44:31 +01:00
Florent Kermarrec 869cce2bba targets/colorlight_5a_75x: rename etherbone-ip args to eth-ip. 
eth-ip will also be used to configure Ethernet IP addresss.
 2021-01-07 09:26:38 +01:00
Florent Kermarrec c829a47c31 targets/colorlight_5a_75x: Automatically disable Led Chaser when serial is used. 2021-01-07 09:17:28 +01:00
enjoy-digital adbcc81ecf
Merge pull request #145 from hansfbaier/master 
colorlight: Add option for etherbone ip address and LED chaser
 2021-01-07 09:08:43 +01:00
enjoy-digital a6e867c691
Merge pull request #144 from gsomlo/gls-genesys2-sdcard 
genesys2: LiteSDCard support
 2021-01-07 08:12:24 +01:00
enjoy-digital d2d17e00a2
Merge pull request #142 from geertu/master 
platforms/ecp5: Fix slewrate configuration
 2021-01-07 08:11:30 +01:00
Florent Kermarrec d73bd2f7ce targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
Florent Kermarrec 1ac1c6857f targets/xilinx: add false path constraint between sys_clk and pll.clkin. 
The SoC reset added recently creates a path between sys_clk and pll.clkin
clock domains that is reported by the tools but that can be safely ignored.
 2021-01-07 00:02:46 +01:00
Hans Baier 0d69cfa6b0 colorlight: make LEDs optional 2021-01-05 08:03:26 +07:00
Hans Baier 4bec17e1a7 colorlight: Add option for etherbone ip address 2021-01-05 07:49:44 +07:00
Gabriel Somlo 2589d9f704 genesys2: add (spi-)sdcard build options 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2021-01-04 13:57:21 -05:00
Gabriel Somlo 4eb0026a69 genesys2: add "rst" and "cd" signals to (spi-)sdcard records 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2021-01-04 13:10:13 -05:00
Geert Uytterhoeven 4a95b94dbf platforms/ecp5: Fix slewrate configuration 
When building linux-on-litex-vexriscv for OrangeCrab:

    Warning: IOBUF 'spisdcard_clk' attribute 'SLEW' is not recognised (on line 207)
    Warning: IOBUF 'spisdcard_mosi' attribute 'SLEW' is not recognised (on line 210)
    Warning: IOBUF 'spisdcard_cs_n' attribute 'SLEW' is not recognised (on line 214)
    Warning: IOBUF 'spisdcard_miso' attribute 'SLEW' is not recognised (on line 218)

Platforms using litex.build.lattice.LatticePlatform seem to support only
"SLEWRATE", not "SLEW".  Fix the few offenders in the LogicBone and
OrangeCrab platform definitions.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
 2021-01-04 17:08:51 +01:00
Florent Kermarrec 016d75512f test/test_targets: update, remove RUNNING_ON_TRAVIS. 2021-01-04 14:35:45 +01:00
Florent Kermarrec fe67766fb7 targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl). 2021-01-04 11:38:07 +01:00
Florent Kermarrec 0e3c03f2f6 mercury_xu5: remove unneeded cmd_latency=0 (now defaulting to 0). 2021-01-04 10:48:34 +01:00
Florent Kermarrec 5cc49bafbd orangecrab: Run reset_timer with por/48MHz clock domain (sys clock domain is now directly reseted on usr_btn press). 2021-01-04 09:42:05 +01:00
Florent Kermarrec 1fb24d4c71 orangecrab: Avoid usb clock domain reset on usr_btn press or SoC reset. 
Allows the USB-ACM link to stay up during reset.
 2021-01-04 09:05:19 +01:00
Florent Kermarrec 06cb49af37 targets/arty: add variant support through --variant args. 
./arty.py --variant=a7-35 or a7-100
./arty_s7.py --variant=s7-50 or s7-25
 2020-12-29 18:43:14 +01:00
Florent Kermarrec 02a81d54e2 targets/ecpix5/eth: set rx_delay to 0ns (tested with netboot on R01). 2020-12-29 16:01:12 +01:00
Florent Kermarrec 93779ecb95 platforms/colorlight_5a_75b: revert toolchain args. 
Useful to do tests with Diamiond.
 2020-12-29 14:22:42 +01:00
enjoy-digital f2985f1e71
Merge pull request #141 from la6m/Colorlight_v8.0 
add colorlight v8.0 PCB
 2020-12-29 14:20:29 +01:00
Florent Kermarrec 84098d2de5 targets/qmtech_wukong: submitted target was the platform file, update with target shared in #133. 
Build tested with /qmtech_wukong.py --with-sdcard --with-ethernet --integrated-rom-size=0x10000 --build.
 2020-12-29 14:13:11 +01:00
Florent Kermarrec b67b18caad qmtech_wukong: review/cleanup platform. 2020-12-29 14:10:49 +01:00
la6m 3e6b934961 add colorlight v8.0 PCB 2020-12-29 13:52:13 +01:00
Florent Kermarrec e380f24655 targets/qmtech_wukong: +x. 2020-12-29 13:24:41 +01:00
Shinken Sanada 4b721eded7 add QmTech Wukong board support. 2020-12-29 13:20:42 +01:00
Florent Kermarrec 9beaf25822 nexys4ddr: fix eth/int_n pin (B8) and use 4-bit on vga.blue. 2020-12-24 10:15:29 +01:00
enjoy-digital 4162fb9945
Merge pull request #136 from devobliquezer0/nexys4ddr_vga 
nexys4ddr: add support for litexvideo VGA Terminal
 2020-12-24 10:09:32 +01:00
Sahaj Sarup 2a04c5c74e nexys4ddr: add support for litexvideo VGA Terminal 
This commit adds VGA support for the Nexys A7/ Nexys 4 DDR.

The VGA is however limited to RGB443 instead of the full 12bit RGB444.
This is because IO D8 which is MSB for Blue, is also used for ETH int_n.
This makes the final output have a yellow tint.
 2020-12-23 02:24:18 +05:30
enjoy-digital 36b7fb1033
Merge pull request #134 from Disasm/fix-orangecrab 
Fix FPGA reset logic for orangecrab target
 2020-12-21 08:27:26 +01:00
Vadim Kaushan f6a106cdf4
Fix orangecrab target 2020-12-20 01:07:43 +03:00
Florent Kermarrec e1f9fd1a25 README: update and center banner. 2020-12-17 18:55:13 +01:00
Florent Kermarrec 00fc2c5166 targets/orangecrab: use new DM remapping capability of LiteDRAM to fix LDM/UDM. 
Required by VexRiscv-SMP that uses DMs on LiteDRAM interface.
 2020-12-16 11:52:58 +01:00
enjoy-digital 6ece97ec59
Merge pull request #132 from Disasm/fix-de10nano 
Fix de10nano target
 2020-12-14 19:39:20 +01:00
Vadim Kaushan bb58258fd4
Fix de10nano target 2020-12-14 15:27:33 +03:00
Florent Kermarrec ec4ccc9fa5 platforms/xcu1525: fix ddram 1/2/3 pinout. 
DDR4 now validated successfully with LiteDRAM on the 4 channels.
 2020-12-11 13:58:26 +01:00
Florent Kermarrec 519f9449fa targets/sds1104: litex_term now directly supports crossover uart. 2020-12-10 13:56:01 +01:00
enjoy-digital 3463e3be49
Merge pull request #131 from antmicro/sync_arty 
Sync Arty Board files with main LiteX repository
 2020-12-07 21:43:34 +01:00
Robert Winkler 18337cdf25 targets/arty: sync with litex repository 
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
 2020-12-07 17:32:40 +01:00
enjoy-digital 0b8a01f929
Merge pull request #130 from antmicro/fix-zybo-clock-pin 
zybo_z7: fix clock pin constraint
 2020-12-07 17:13:40 +01:00
Alessandro Comodi f66860c201 zybo_z7: fix clock pin constraint 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-12-07 16:46:20 +01:00