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1094 Commits

Author SHA1 Message Date
Florent Kermarrec 4f7c18a503 mnt_rkx7: Add Ethernet/Etherbone support. 2021-09-30 15:14:03 +02:00
Florent Kermarrec 84f0d715ff mnt_rkx7: Add SDCard support. 2021-09-30 11:34:23 +02:00
Florent Kermarrec 31b404c42f mng_rkx7: Add SPI Flash support. 2021-09-30 11:29:56 +02:00
Florent Kermarrec df7fe5687e Add initial MNT Reform Kintex-7 module (RKX7) support with Clk, UART and DDR3. 
Compiles but untested on hardware.
 2021-09-30 11:06:39 +02:00
Florent Kermarrec 82653cf66f icebreaker/fomu: Fix SPRAM split. 2021-09-30 09:32:26 +02:00
Florent Kermarrec 5addd7f7d8 icebreaker/fomu: Split PSRAM in half: 64kB SRAM/64kB RAM). 
Allows building bare metal demo and running it directly on these boards.
 2021-09-29 19:33:22 +02:00
enjoy-digital dfa572083a
Merge pull request #273 from ozbenh/wukong-v2 
Wukong board improvements
 2021-09-28 13:22:42 +02:00
Florent Kermarrec 2089c2b708 ci: Install meson (now required by picolibc). 2021-09-27 16:21:43 +02:00
Alessandro Comodi 228245075a boards: added datacenter DDR4 RDIMM tester board 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-09-27 10:15:55 +02:00
Benjamin Herrenschmidt 4a52996106 Wukong board improvements 
This adds support for v2 of the board via a --board-version argument
and a way to select the FPGA speed grade via a --speed-grade argument.

Note that the speed grade now defaults to -1. QMTech confirmed that
V1 of the board were made in two batches, one with -1 and one with -2,
while V2 of the board is all -1. So -1 is the safer default.

This also fixes the inversion of j10 and j11 and a typo in the pin
definition of jp3

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2021-09-24 12:13:56 +10:00
enjoy-digital f18b10d1ed
Merge pull request #249 from Quiddle11/atlys 
Initial Digilent Atlys support
 2021-09-23 10:21:49 +02:00
Florent Kermarrec 921c300b50 digilent_atlys: Simplify/Remove entropy... 
Build tested with ./digilent_atlys.py --with-ethernet --build.
 2021-09-23 10:17:54 +02:00
enjoy-digital 7778f1fc93
Merge pull request #272 from alainlou/master 
rz_easyfpga: adjust SDRAM clk phase, also add 1:2 rate
 2021-09-23 09:01:17 +02:00
alainlou 1333f89ed6 rz_easyfpga: adjust SDRAM clk phase 
- also add 1:2 rate
 2021-09-22 00:26:28 -04:00
Alain Lou 610e82d774
Add initial RZ-EasyFPGA support! (#270) 2021-09-21 09:55:22 +02:00
Florent Kermarrec d5eea94289 sispeed_tang_nano_4k: Avoid IOStandard constraints on HyperRAM (Not present in example designs). 2021-09-20 11:46:10 +02:00
Florent Kermarrec 5190c9c869 sipeed_tang_nano_4k: Initial Video Out support. 
With colorbars for now, need to free up BRAMS for Video Terminal (or finish HyperRAM support).
 2021-09-20 09:32:20 +02:00
Florent Kermarrec 30756ce05e targets: Update to VideoHDMIPHY. 2021-09-20 09:30:32 +02:00
Florent Kermarrec 7161ad18ec sipeed_tang_nano_4k: Integrate new LiteX's GW1NSRPLL. 2021-09-20 08:40:19 +02:00
Florent Kermarrec a5c5ba7652 sipeed_tang_nano_4k: Integrate HyperRam (not yet working). 2021-09-17 16:30:39 +02:00
Florent Kermarrec 376a836583 sipeed_tang_nano: Add SPI Flash, Enable CPU and use new external SPI Flash support from OpenFPGALoader. 
./sipeed_tang_nano_4k.py --cpu-type=vexriscv --cpu-variant=lite --build --flash

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2021 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Sep 17 2021 15:54:08
 BIOS CRC passed (6cc6de6d)

 Migen git sha1: a5bc262
 LiteX git sha1: 46cd9c5a

--=============== SoC ==================--
CPU:		VexRiscv_Lite @ 27MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		64KiB
SRAM:		8KiB
FLASH:		4096KiB

--========== Initialization ============--

Initializing W25Q32 SPI Flash @0x80000000...
SPI Flash clk configured to 13 MHz
Memspeed at 0x80000000 (Sequential, 4.0KiB)...
   Read speed: 1.3MiB/s
Memspeed at 0x80000000 (Random, 4.0KiB)...
   Read speed: 521.9KiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
 2021-09-17 15:57:55 +02:00
Florent Kermarrec 28571308bc sispeed_tang_nano: Add simple UART loopback test... (Not working...) 2021-09-16 19:34:48 +02:00
Florent Kermarrec 5955a35372 Add initial Sipeed Tang Nano support (Clk/Leds/Buttons). 2021-09-16 19:22:30 +02:00
Florent Kermarrec c0aed8a727 litex_m2_baseboard: Add Video Terminal support. 2021-09-16 18:54:50 +02:00
Florent Kermarrec 32a9256f3b litex_m2_baseboard: Add SDCard support. 2021-09-16 18:17:34 +02:00
Florent Kermarrec 0854a5d234 litex_m2_baseboard: Add Ethernet/Etherbone support. 2021-09-16 18:02:55 +02:00
Florent Kermarrec 8d2f75ca6d litex_m2_baseboard: Add PMODs connectors. 2021-09-16 17:48:53 +02:00
Florent Kermarrec 3ad0eb6992 Add initial LiteX M2 Baseboard support with Clk/Serial/Buttons. 2021-09-16 17:44:50 +02:00
Tim Ansell 67756e53ae
Merge pull request #269 from kammoh/readme_zybo_fpga 
Update README.md
 2021-09-15 07:34:20 -07:00
Kamyar Mohajerani b75af2f21c
Update README.md 
FPGA on "Zybo Z7" is a 7-Series Zynq not a Zynq Ultrascale+
 2021-09-15 10:21:10 -04:00
Florent Kermarrec 078b1ed7b7 CONTRIBUTORS: Update. 2021-09-15 14:59:42 +02:00
enjoy-digital 26943959b5
Merge pull request #268 from trabucayre/runber_support 
Add runber support
 2021-09-15 08:32:05 +02:00
enjoy-digital 1ca77d6921
Merge pull request #267 from trabucayre/tangnano4k_fix_period 
platforms/sipeed_tang_nano_4k: fix period computation
 2021-09-15 08:28:19 +02:00
Gwenhael Goavec-Merou 7ccae3332d Add runber support 2021-09-15 06:50:57 +02:00
Gwenhael Goavec-Merou fed36afaba platforms/sipeed_tang_nano_4k: fix period computation 2021-09-15 06:46:29 +02:00
Florent Kermarrec 68fb163a27 targets: Remove spiflash mapping on targets where it's no longer useful. 2021-09-14 18:35:13 +02:00
Florent Kermarrec db91eda899 linsn_rv901t.py: Update Ethernet and add Etherbone support. 2021-09-13 19:35:05 +02:00
enjoy-digital b9f2a4c483
Merge pull request #266 from teknoman117/mojov3 
Add Mojo V3 support
 2021-09-10 14:01:59 +02:00
Nathaniel R. Lewis b8373a361d alchitry_mojo: new board 2021-09-10 02:40:31 -07:00
enjoy-digital d4613562a8
Merge pull request #265 from trabucayre/tangNano4K_connector 
platforms/sipeed_tang_nano_4k: add P6 and P7 connectors
 2021-09-09 11:43:05 +02:00
enjoy-digital cacb76450f
Merge pull request #264 from teknoman117/alchitry-au 
Add Alchitry Au as new board
 2021-09-09 11:42:37 +02:00
Florent Kermarrec 3622661fa8 test/test_targets: Remove build directory before build. 2021-09-09 11:36:18 +02:00
Gwenhael Goavec-Merou 945e48ea83 platforms/sipeed_tang_nano_4k: add P6 and P7 connectors 2021-09-09 11:35:14 +02:00
Florent Kermarrec 8d91489756 tang_nano_4k: Add more IOs. 2021-09-09 11:23:20 +02:00
Nathaniel R. Lewis 9bbdb87130 alchitry_au: new board 2021-09-09 00:03:19 -07:00
Florent Kermarrec 88534c6689 tang_nano_4k: Fix typo in sipeed. 2021-09-08 23:02:39 +02:00
Florent Kermarrec ce52c8c5ed beaglewire: Fix typo in qwertyembedded. 2021-09-08 21:29:29 +02:00
Florent Kermarrec ecebe7e267 Add initial SiSpeed Tang Nano 4K support (Led blink only for now...). 
./sispeed_tang_nano_4k.py --build --load

Build with Gowin EDA.
Load with OpenFPGALoader.
 2021-09-08 19:36:46 +02:00
Florent Kermarrec 129b95f9b5 sqrl_acorn: Update pre_placement_commands with new XilinxVivadCommands. 2021-09-08 16:27:30 +02:00
Florent Kermarrec 7fa22a494b arty: Switch SPI Flash rate to 1:2 (DDR) (Possible on Arty since SPI Flash's clk does not require use of STARTUPE2). 
On the Digilent Arty, the SPI Flash's clk is connected to CCLK (that can be driven
through the STARTUPE2) but also to another generic IO that can be use to drive the
clock through DDR primitives.
 2021-09-07 15:07:59 +02:00