Florent Kermarrec
|
30ea463b41
|
targets: keep attributes are no longer needed since automatically added when applying constraints to signals.
|
2019-12-06 16:01:59 +01:00 |
|
Florent Kermarrec
|
f7fbfb4639
|
partner/community/targets: uniformize, improve presentation
|
2019-12-03 09:33:08 +01:00 |
|
Florent Kermarrec
|
2a0fbcadd2
|
ac701: add pcie_x1 pins
|
2019-11-06 09:29:55 +01:00 |
|
Florent Kermarrec
|
1ae26dd499
|
targets: use type="io" instead of io_region=True
|
2019-10-30 16:35:32 +01:00 |
|
Florent Kermarrec
|
785909ac5f
|
targets: switch from shadow_base to io_regions
|
2019-10-09 11:09:59 +02:00 |
|
Florent Kermarrec
|
b4eefa6c33
|
import: allow importing directly from litex_boards.platforms or litex_boards.targets
|
2019-09-03 15:30:20 +02:00 |
|
Florent Kermarrec
|
e704014b36
|
targets/__init__: comment targets import until we found a way to avoid litedram/liteeth dependecies for targets no using them.
|
2019-09-01 11:43:21 +02:00 |
|
Florent Kermarrec
|
f661ee0ec9
|
targets: fix import
|
2019-08-26 11:00:12 +02:00 |
|
Florent Kermarrec
|
ac58d57a83
|
targets: import platforms from litex_boards.platforms
|
2019-08-26 09:09:40 +02:00 |
|
Florent Kermarrec
|
b84308cb58
|
list all platforms/targets in platforms.py, targets.py to ease import
|
2019-08-26 09:07:07 +02:00 |
Arnaud Durand
|
618f41bb1e
|
Update ecp5_evn.py
The system clock was driven directly while it should be driven by the PLL.
|
2019-08-22 02:27:50 +02:00 |
|
DurandA
|
1abca7dcff
|
Turn litex_boards.community into module
|
2019-08-12 00:17:26 +02:00 |
|
enjoy-digital
|
ad21f15782
|
Merge pull request #10 from DurandA/ecp5-evn
Add ECP5 Evaluation Board
|
2019-08-09 12:37:36 +02:00 |
|
DurandA
|
c90950e319
|
Default to 60 Mhz system clock on ECP5 Evaluation Board
Exact PLL clock can be derived from U1 12 Mhz or X5 50 Mhz clock.
|
2019-08-09 11:58:30 +02:00 |
|
DurandA
|
9e6dccc277
|
Remove ECP5 Evaluation Board programmer
|
2019-08-09 11:54:49 +02:00 |
|
DurandA
|
4126ed21d5
|
Add X5 clock and PLL to ECP5 Evaluation Board
|
2019-08-09 11:54:38 +02:00 |
|
DurandA
|
c7444fe19c
|
Add ECP5 Evaluation Board
|
2019-08-09 09:45:13 +02:00 |
|
Florent Kermarrec
|
9f3ed82097
|
keep up to date with LiteX
- use 1e9/freq for default_clk_period
- add default serial on tinyfpga_bx
- use S6PLL on minispartan6
- add SPIFlash pins on versa_ecp5
|
2019-08-07 08:47:08 +02:00 |
|
Florent Kermarrec
|
a88970a67f
|
move trellis board from community to partner
|
2019-07-12 19:23:21 +02:00 |
David Shah
|
a07e88d761
|
community: Add TrellisBoard
Signed-off-by: David Shah <dave@ds0.me>
|
2019-07-09 15:52:28 +01:00 |
|
Florent Kermarrec
|
aeddb93729
|
add copyright header to all files, udpate.
|
2019-06-24 12:13:54 +02:00 |
|
Florent Kermarrec
|
44d01edab9
|
dispatch platforms/targets by level of support
|
2019-06-10 18:59:49 +02:00 |
|
Florent Kermarrec
|
4213c75e48
|
init repo with litex official boards
|
2019-06-10 17:11:36 +02:00 |