27f60b2e93
add initial Siglent SDS1104X-E support (Ethernet & DDR3 validated).
...
Pinout from https://github.com/360nosc0pe project.
2020-11-13 12:20:15 +01:00
843e724e3d
targets/pcie: simplify using new LiteX's add_pcie method and enable it on all devices supported by LitePCIe.
2020-11-12 16:39:42 +01:00
9f11bfb0d1
qmtech_ep4ce15: convert name to lowercase, minor cleanup and add to test_targets.
2020-11-12 14:33:45 +01:00
31eb74dc2d
Merge pull request #122 from baselsayeh/master
...
add Qmtech EP4CE15 coreboard support
2020-11-12 14:27:49 +01:00
46e8a957fe
platforms/zybo_z7: fix default_clk typo.
2020-11-12 14:26:36 +01:00
ac075f18c7
platforms/crosslink_nx_evn/vip: add default_clk.
2020-11-12 14:26:17 +01:00
0fc67ddfdb
update copyright
2020-11-12 15:25:39 +02:00
a4d05522d4
platforms/ice40/ecp5: add toolchain parameter with default to trellis (ECP5) or icestorm (iCE40).
...
Required to simplify simple.py target and use trellis/icestorm as default toolchain.
2020-11-12 13:33:30 +01:00
1b1ed5ebf1
add Qmtech EP4CE15 coreboard support
2020-11-12 01:56:36 +02:00
97b64d16a6
Lattice NX PLL Support
2020-11-08 20:34:46 -06:00
1f52fbaca6
xcu1525: fix last ddram channel numbering.
2020-11-06 10:48:26 +01:00
2da4eabffe
platforms/icebreaker: fix refactoring typo.
2020-11-04 09:30:01 +01:00
c093d0d0fc
platforms: cleanup pass to uniformize comments/separators/orders.
2020-11-03 10:48:57 +01:00
d1c9cc7553
Add LFE5U-12F device for ULX3S
2020-11-01 23:45:32 +00:00
d626861e95
platforms/acorn_cle_215: add serial_io (on P2).
2020-10-29 12:10:12 +01:00
51934567fe
Merge pull request #118 from daveshah1/lifcl-vip
...
Add CrossLink-NX VIP board platform and target
2020-10-22 11:03:47 +02:00
a38c1e7062
mist: add copyrights.
2020-10-22 10:48:58 +02:00
20720693c4
crosslink_nx_vip: Add HyperRAM support
...
Signed-off-by: David Shah <dave@ds0.me>
2020-10-22 09:15:40 +01:00
b278d8bccc
Add CrossLink-NX VIP board platform and target
2020-10-22 09:15:35 +01:00
4541c39e94
Initial support for the MIST board ( https://github.com/mist-devel/mist-board/wiki )
2020-10-17 12:28:22 +02:00
982cfd5ad5
platforms/xcu1525: fix ddram constraints, add clk300 constraints for all channels.
2020-10-13 11:50:36 +02:00
ddf7038c78
ulx3s: add 1.7 and 2.0 revisions support.
2020-10-12 13:23:26 +02:00
3b11e60fb1
Update ULX3S SD pins for revision 2.0
2020-10-11 14:17:48 +11:00
55da8b867a
platforms/zedboard: minor cleanups to uniformize with other platforms.
2020-10-07 11:25:20 +02:00
e225cbd28f
add zedboard platform to CI
2020-10-06 11:35:03 -07:00
8ee20a3f30
clean up imports
2020-10-06 11:24:34 -07:00
865c2bd98c
zedboard platform: clean up
...
* remove unused code
* remove oled integration code
* openocd = default programmer
2020-10-06 11:00:36 -07:00
12aed44577
add zedboard platform
2020-10-06 00:28:54 -07:00
79ef091a06
Merge pull request #110 from pepijndevos/gowin
...
Add initial support for Trenz TEC0117 board
2020-10-05 19:50:09 +02:00
2ee32f2a15
Merge pull request #109 from geertu/orangecrab-Fix-r0.1-user_led-mapping
...
orangecrab: Fix r0.1 user_led mapping
2020-10-02 09:40:41 +02:00
062fbd6c63
Merge pull request #108 from daveshah1/dave/nx-evn-doc
...
crosslink_nx_evn: Improve documentation on UART jumpers
2020-10-02 09:40:04 +02:00
81e4f1f158
add initial support for Trenz TEC0117 board
2020-09-30 14:01:36 +02:00
b2e34f5faf
orangecrab: Fix r0.1 user_led mapping
...
On r0.1, all three user_leds are mapped to the same pin.
Fix this by mapping them to the pins connected to the individual
channels of the RGB LED, to match the comments, the schematics, and the
spirit of r0.2.
Untested on real hardware (I have r0.2 only).
Fixes: c94cbae0c0
2020-09-25 10:33:21 +02:00
c6610b4a3f
platforms/xcu1525: update ddram1/2/3 pinout.
...
Using https://github.com/d953i/Custom_Part_Data_Files/blob/master/Boards/Xilinx_BCU1525/BCU1525_DIMMx.xdc
2020-09-20 21:07:00 +02:00
e5a144e9cd
platforms/xcu1525: update ddram0 pinout.
...
Using https://github.com/d953i/Custom_Part_Data_Files/blob/master/Boards/Xilinx_BCU1525/BCU1525_DIMM0.xdc .
2020-09-19 23:28:34 +02:00
8ffb86c0dc
platforms/fk33/xcu1525: define pcie_x2/x4/x8/x16.
2020-09-19 22:37:05 +02:00
8a9fd02768
crosslink_nx_evn: Improve documentation on UART jumpers
...
Signed-off-by: David Shah <dave@ds0.me>
2020-09-05 09:58:28 +01:00
76ac4a69a8
rename forest_kitten_33 platform/target to fk33.
2020-09-04 20:05:18 +02:00
979fee7517
forest_kitten_33: add pcie.
2020-09-04 20:02:43 +02:00
ad48728160
xcu1525: update headers (were still using old format).
2020-09-04 19:59:09 +02:00
ad4c483c32
Merge pull request #106 from daveshah1/dave/alveo_u250_pcie
...
alveo_u250: Add PCIe x4 support
2020-09-04 19:22:48 +02:00
a68c00e48e
Merge pull request #104 from DerFetzer/colorlight_5a_75e_v6_0
...
Add support for 5A-75E V6.0 board
2020-09-04 19:21:02 +02:00
ae6a052e57
alveo_u250: Add PCIe x4 support
...
Based on the implementation in xcu1525
Signed-off-by: David Shah <dave@ds0.me>
2020-09-04 14:20:04 +01:00
2eda9d0252
xcu1525: add DDR4 IOs for C1/C2/C3 and fix compilation (untested).
2020-09-04 11:34:33 +02:00
7b6b71d4e3
xcu1525: add initial DDR4 support in C0 (untested).
2020-09-03 19:48:23 +02:00
51e881d1ff
add minimal xcu1525 support (VCU1525 or BCU1525 boards).
2020-09-03 19:06:43 +02:00
cc78574297
targets/colorlight_5a_75x: fix rx_data pin order for Ethernet PHY 0
2020-09-02 22:04:23 +02:00
8b1fee0e66
Add support for 5A-75E V6.0 board
2020-09-01 17:02:17 +02:00
beccecf59f
orangecrab: reduce DDR3 power consumption/heat and get back USB PLL to CRGSDRAM.
...
- disable DQ termination.
- disable RTT_NOM.
- drive VCCIO/GND pads.
Reduce current from 0.25A to 0.12A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=48e6.
Still working at 96MHz, 0.17A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=96e6.
See https://github.com/enjoy-digital/litedram/issues/216 .
2020-08-28 20:01:54 +02:00
63b65e278c
crosslink_nx_evn: update copyrights.
2020-08-24 22:33:58 +02:00
Florent Kermarrec
Basel Sayeh
davidcorrigan714
Kevin Mehall
David Shah
YanekJ
Bryan Jacobs
Michael Betz
Pepijn de Vos
Geert Uytterhoeven
DerFetzer