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675 Commits

Author SHA1 Message Date
enjoy-digital 35e0026875
Merge pull request #303 from sergachev/master 
sipeed_tang_nano_4k: add option to build with Gowin EMCU
 2021-12-09 14:30:54 +01:00
Ilia Sergachev 14a8c50e97 sipeed_tang_nano_4k: connect Gowin EMCU UART, undo unnecessary changes 2021-12-09 00:17:48 +01:00
Ilia Sergachev 6274c4c425 sipeed_tang_nano_4k: connect Gowin EMCU UART 2021-12-09 00:12:31 +01:00
Ilia Sergachev 13c83ba532 sipeed_tang_nano_4k: add initial Gowin EMCU support 2021-12-08 23:50:14 +01:00
Ilia Sergachev 4287ab561e sipeed_tang_nano_4k: allow non-vexriscv CPUs 2021-12-08 23:33:49 +01:00
enjoy-digital 9119250276
Merge pull request #300 from tilk/de1_soc 
Better support for DE1-SoC
 2021-12-08 06:18:25 +01:00
enjoy-digital 2b7587632f
Merge pull request #299 from gregdavill/butterstick-updates 
Butterstick updates
 2021-12-08 06:16:29 +01:00
Florent Kermarrec 8ad89881c2 fairwaves_xtrx: Add pcie_x2 definitions and switch to it. 2021-12-07 15:27:55 +01:00
Marek Materzok cbeb2a3792 Add LedChaser to DE1-SoC 2021-12-05 20:16:10 +01:00
Greg Davill fd2ec534a7 butterstick: Add extra pins 2021-12-05 20:33:28 +10:30
Greg Davill c8a8e943b5 butterstick: add --sdram-device option 
Set 64M16 as default sdram-device.

Related to #298
 2021-12-04 17:07:06 +10:30
Florent Kermarrec bf8b23c19f trenz_tec0117: Update target. 2021-12-02 18:23:11 +01:00
enjoy-digital efa1f46356
Merge pull request #297 from sergachev/master 
Fix Sipeed Tang Nano 4k example compilation; adapt Gowin PLL class changes
 2021-12-02 09:14:32 +01:00
Ilia Sergachev 666ef9dad3 sipeed_tang_nano_4k: use minimal vexriscv variant to fit into number of BSRAMs 2021-11-29 11:46:32 +01:00
Ilia Sergachev 2fb734a0f2 sipeed_tang_nano*: adapt Gowin PLL changes in litex 2021-11-29 11:45:13 +01:00
Florent Kermarrec 1829693877 fairwaves_xtrx: Integrate ICAP/SPIFlash (for update over PCIe). 2021-11-26 16:18:52 +01:00
enjoy-digital fe14e16c1b
Merge branch 'master' into tang_primer 2021-11-23 19:04:09 +01:00
Miodrag Milanovic 6954dd25eb Set minimal core, since full does not work for some reason 2021-11-23 15:26:54 +01:00
Miodrag Milanovic 0b7fabb864 FireAnt board support 2021-11-23 14:43:52 +01:00
Miodrag Milanovic 2cc322e65d Add initial support for Tang Primer board 2021-11-22 19:10:11 +01:00
Florent Kermarrec 70c0dbb185 targets/radiona_ulx3s: Remove SDRAM underflows debug pin. 2021-11-22 11:54:18 +01:00
Florent Kermarrec 60b769b624 efinix_trion_t120_bga576_dev_kit/ethernet: Disable software debug (RX now seems to be working fine). 2021-11-16 18:53:15 +01:00
Florent Kermarrec 996f5b2edd efinix_trion_t120_bga576_dev_kit: Enable target1 port and also connect it to SoC. 2021-11-16 18:12:42 +01:00
Florent Kermarrec 7ce6c4cf79 efinix_trion_t120_bga576_dev_kit: Switch to ctrl_type = "none" (Also seems to work fine, avoid ddr_reset_sequencer dependency). 2021-11-16 17:50:47 +01:00
Florent Kermarrec 99f4f97f00 efinix_trion_t120_bga576_dev_kit: Use new InterfaceWriterBlock/InterfaceWriterXMLBlock and move PLL/DRAM blocks definition to target. 2021-11-16 17:41:26 +01:00
Hans Baier e16fa193fc qmtech 10cl006: remove all options which won't fit into the device. use uartbone as default 2021-11-15 10:23:01 +07:00
Florent Kermarrec 138dc1467e quicklogic_quickfeather: Fix build with GPIOIn when cpu-type=None (IRQ not supported). 2021-11-14 09:30:52 +01:00
Florent Kermarrec ed67b91fcc quicklogic_quickfeather: Simplify cpu_type switch between None/EOS-S3. 2021-11-14 09:26:29 +01:00
Florent Kermarrec 2d3422869c quicklogic_quickfeather: Update clocking. 2021-11-14 09:19:19 +01:00
Florent Kermarrec df468fcf85 quicklogic_quickfeather: Avoid add_csr calls (not required). 2021-11-14 08:54:49 +01:00
Florent Kermarrec 06bae58f48 efinix_trion_t120_bga576: Do a bit a of cleanup on LPDDR3 now that working. 2021-11-12 19:43:28 +01:00
Florent Kermarrec 86f6d7e66b efinix_trion_t120_bga576_dev_kit: Remove test command. 2021-11-12 18:06:11 +01:00
Florent Kermarrec 4e03f66fad efinix_trion_t120_bga576_dev_kit: Remove debug, integrate LPDDR3 as done on other targets. 
Also lower sys_clk_freq since seems to cause issue with DRAM at 100MHz: Needs to be investigated.
 2021-11-12 18:04:30 +01:00
Florent Kermarrec 77fffda9cd efinix_trion_t120_bga576_dev_kit: Switch to UARTBone, Add LiteScope on Pseudo-AXI, fix addressing and do first successful LPDDR3 accesses :) 2021-11-12 16:41:42 +01:00
Gwenhael Goavec-Merou 648d38da7e quicklogic_quickfeather: add button and GPIOIn 
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
 2021-11-12 13:21:00 +01:00
Florent Kermarrec b6c5a85b98 Add initial Efinix Trion T20 MIPI Dev Kit support: CPU, ROM, RAM, UART and SPI Flash. 
Tested with:
./efinix_trion_t20_mipi_dev_kit.py --with-spi-flash --build --load
        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2021 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Nov 12 2021 08:37:48
 BIOS CRC passed (2bec12a3)

 Migen git sha1: 7507a2b
 LiteX git sha1: f679992f

--=============== SoC ==================--
CPU:		VexRiscv @ 100MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128KiB
SRAM:		8KiB
FLASH:		4096KiB

--========== Initialization ============--

Initializing W25Q32JV SPI Flash @0x00400000...
Enabling Quad mode...
First SPI Flash block erased, unable to perform freq test.
Memspeed at 0x400000 (Sequential, 4.0KiB)...
   Read speed: 2.6MiB/s
Memspeed at 0x400000 (Random, 4.0KiB)...
   Read speed: 1.5MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
 2021-11-12 08:42:10 +01:00
Florent Kermarrec d6fc4b412e efinix_trion_t120/t20_dev_kit: Switch back to 100MHz (now that timings constraints are correctly applied). 2021-11-12 07:58:51 +01:00
Florent Kermarrec 7ce8567d9b targets/efinix: Bitstreams now directly generated to gateware directory. 2021-11-11 11:19:39 +01:00
Florent Kermarrec 855fd7e3d7 efinix_trion_t120_bga576_dev_kit: Continue LPDDR3 integration... 2021-11-10 19:40:35 +01:00
Florent Kermarrec 224f527baa efinix_trion_t120_bga576_dev_kit: Go a bit further in DRAM integration. 2021-11-10 12:07:30 +01:00
Gwenhael Goavec-Merou 040e7b3104 quicklogic_quickfeather: Use initial EOS-S3 support/integration. 2021-11-09 18:59:37 +01:00
Florent Kermarrec 8ce83ce92f efinix_trion_t120_bga576_dev_kit: Add inital LPDDR3 integration (not yet working). 2021-11-09 16:13:40 +01:00
Florent Kermarrec 9a7e5f40b4 efinix_trion_t120_bga576_dev_kit: Add Ethernet/Etherbone support. 
Still not fully validated: TX seems OK but RX seems shifted/corrupted.
 2021-11-09 11:32:32 +01:00
Florent Kermarrec ccebae6f55 targets/hyperram: Update integration. 2021-11-08 16:39:49 +01:00
Florent Kermarrec 184f41e61a sipeed_tang_nano: Use PLL and 48MHz sys_clk, switch to SoCMini, add UARTBone (at 1MBauds). 
Working correctly on hardware with updated CH552 firmware & patched litex_server...
 2021-11-08 09:23:44 +01:00
Hans Baier d6bf2fd00e terasic_sockit: Use standard SDRAM module from litedram 2021-11-08 12:48:03 +07:00
Hans Baier a9847f15a7 qmtech_5cefa2: tuned the clock phase shift to be able to run the system at 105MHz 2021-11-06 09:58:10 +07:00
Hans Baier b2813cfb70 use the right DRAM chip for the QMTech Altera boards 2021-11-06 08:45:03 +07:00
Florent Kermarrec 6e7c76b71e fairwaves_xtrx: Add clk60 (from USB PHY) as default Clk when no PCIe. 
Fixes CI.
 2021-11-05 15:22:55 +01:00
Florent Kermarrec ceaaf67dfd Add initial Fairwaves XTRX support (SoC with JTAG-UART and PCIe Gen2 X1). 2021-11-05 14:52:45 +01:00