Commit Graph

17 Commits

Author SHA1 Message Date
Gwenhael Goavec-Merou a6f3c5276e target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
Florent Kermarrec f400179b5b targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
Florent Kermarrec 58489ebebf targets/BaseSoC: Cleanup parameters. 2022-11-08 12:31:49 +01:00
Florent Kermarrec 9e7079c4c8 targets: Remove int() on BaseSoC's sys_clk_freq. 2022-11-08 11:54:17 +01:00
Florent Kermarrec b0e6414519 targets: Cleanup arguments and switch --sys-clk-freq to float (avoid conversion in code). 2022-11-08 10:41:35 +01:00
Florent Kermarrec 16b9677acd targets: Switch to soc_core_argdict.
The next move was to remove soc_core and only keep soc; so this is probably the right time to do
it in targets to avoid having to handle it later.
2022-11-07 08:43:26 +01:00
Florent Kermarrec 33b0400aed targets: Update LiteXArgumentParser imports. 2022-11-06 21:39:52 +01:00
Gwenhael Goavec-Merou 9960f38d95 targets: replace LiteXSoCArgumentParser by LiteXArgumentParser, remove tasks done LiteXArgumentParser 2022-11-06 11:27:47 +01:00
Florent Kermarrec 548a028730 targets: Switch to LiteXModule to simplify/cleanup code. 2022-10-27 21:21:37 +02:00
Florent Kermarrec b32969c29f targets/Ultrascale(+): Remove BUFGCE name overrides.
Not required, was only useful on a specific project.
2022-06-10 19:21:04 +02:00
Florent Kermarrec 45494f60e0 targets: Change SoC/Software headers generation behaviour (Now only generated with --build).
Re-generating the SoC/Software headers was causing some un-expected behaviours for users not familiar
with the flow. For example doing a --load with a different configuration, was re-generating the Software
headers and messing up things when trying to run software on the SoC.
2022-05-06 15:14:32 +02:00
Florent Kermarrec a611f035d6 targets: Move CRG before SoCCore init (More logical and simplify some specific reset schemes) and switch SoCCore to one line when possible.
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical.
Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
2022-04-21 12:19:45 +02:00
Florent Kermarrec 00ff61baa9 targets: Simplify clock domains and remove useless reset_less.
rst was not directly assigned/used on reset_less clock domains, so reset_less
property was not really useful. With the changes on stream.CDC, having a rst
(Even fixed at 0) is now mandatory on clock domains involved in the CDC, so this
also fixes targets.
2022-04-01 11:30:38 +02:00
Florent Kermarrec 9d452b0d74 targets: Create target_group for target arguments. 2022-03-21 18:37:40 +01:00
Florent Kermarrec cc8da9d341 targets: Simplify imports and switch to LiteXSocArgumentParser.
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
2022-03-21 16:59:40 +01:00
Florent Kermarrec 773444a7dd targets: Switch to get_bios_filename/get_bitstream_filename. 2022-03-17 09:21:05 +01:00
Sylvain Munaut ec28ca8fa3 adi_adrv2crr: Add support for the ADI ADRV2CRR with ADRV9009-ZU11EG SoM
This is a carrier board with a SoM mounted on it.
There is also an FMC connector that can accept another
AD-FMCOMMS8-EBZ to get two more ADRV9009 RFIC but support for
that is not added yet.

Note that the PCIe support requires :
 - Change the .xci in the litepcie to use the right Quad
 - Revert litex 3c34039b731b42e27e2ee6c8e399e5eb8f3a058f so the
   timing constrainst of litepcie apply correctly

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2022-03-03 22:17:09 +01:00