Commit Graph

18 Commits

Author SHA1 Message Date
Florent Kermarrec 1ca8ef97a1 targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM). 2021-03-29 16:03:19 +02:00
Florent Kermarrec ba01776432 targets/add_sdram: Simplify call by removing useless arguments.
- main_ram mem_map is now directly used by add_sdram when origin is None.
- max_sdram_size/min_l2_data_width are no longer exposed as targets arguments this can
still be used enforced directly in the few cases it is useful.
2021-03-29 15:28:31 +02:00
Florent Kermarrec 47bdf5f759 targets: Use new CSR automatic allocation (self.add_csr will still work but is no longer required). 2021-03-25 10:11:24 +01:00
Florent Kermarrec 5995769b46 targets: Switch to soc_core_args/soc_core_argdict (instead of soc_sdram that is now deprecated, but still supported for now). 2021-03-24 17:22:51 +01:00
Florent Kermarrec 5a4e28d47d target/usb_acm: switch git clone to litex-hub/valentyusb repo (up to date with LiteX). 2020-11-27 18:53:45 +01:00
Florent Kermarrec d42af3ea19 targets: add --sys-clk-freq support to all targets. 2020-11-12 18:07:28 +01:00
Florent Kermarrec bd4e92ad13 targets: cleanup, uniformize build arguments between targets. 2020-11-12 11:46:00 +01:00
Florent Kermarrec 2b17dc1b89 target: add rst signal to CRG to allow full reset of the SoC on reboot command. 2020-11-04 11:13:42 +01:00
Florent Kermarrec c093d0d0fc platforms: cleanup pass to uniformize comments/separators/orders. 2020-11-03 10:48:57 +01:00
Florent Kermarrec 814e7630e4 targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it. 2020-10-13 12:10:29 +02:00
Florent Kermarrec b9ac72cf78 targets: simplify clocking on iCE40/ECP5 targets (AsyncResetSynchronizer now integrated in PLL). 2020-09-01 13:38:32 +02:00
Florent Kermarrec 1781be166a general: add SPDX License identifier to header and specify files are part of LiteX-Boards. 2020-08-23 15:00:17 +02:00
Florent Kermarrec 869ceadacb targets: use platform.request_all on LedChaser. 2020-08-06 20:04:03 +02:00
Florent Kermarrec 7b1bf9d74a targets: remove sdcard specific clock domain (now generated by the PHY). 2020-07-03 20:09:30 +02:00
Florent Kermarrec 31e6997e70 sdcard: rename cd_sdcard to cd_sd to avoid unnecessary clock domain. 2020-07-01 12:58:48 +02:00
Florent Kermarrec 7a48a61605 targets: add indentifier on all targets. 2020-06-30 18:11:04 +02:00
Florent Kermarrec 1356ebb416 targets/ecp5: update clocking on boards with DDR3 to use reset from ddrphy.init and use primary clock for Power on reset. 2020-06-29 16:42:53 +02:00
Owen Kirby 76a32ba8ec Add Logicbone ECP5 board
The Logicbone is an Open Source development board for the Lattice ECP5
being developed at https://github.com/oskirby/logicbone
2020-06-27 03:32:47 -07:00