10 commits

Author	SHA1	Message	Date
Florent Kermarrec	028d4a78aa	targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args	2020-01-13 15:20:37 +01:00
Florent Kermarrec	babbc676eb	targets: cleanup ECP5 CRGs	2020-01-09 14:24:18 +01:00
Florent Kermarrec	1b1370d086	official/targets: uniformize, improve presentation	2019-12-03 09:07:09 +01:00
Florent Kermarrec	91083f99a8	ulx3s: simplify SDRAM module selection	2019-10-13 21:15:22 +02:00
Steven Osborn	abf6f7b09a	memory device selection for ulx3s	2019-10-13 09:27:33 -07:00
Steven Osborn	34507eb431	add sys clock freq flag, uses same method as current versa code	2019-10-13 00:44:07 -07:00
Florent Kermarrec	0ead12bae8	targets/ulx3s: revert to cl=2	2019-09-25 13:58:45 +02:00
Florent Kermarrec	ac58d57a83	targets: import platforms from litex_boards.platforms	2019-08-26 09:09:40 +02:00
Florent Kermarrec	debafd7c17	official/partner: update	2019-07-12 19:19:01 +02:00
Florent Kermarrec	44d01edab9	dispatch platforms/targets by level of support	2019-06-10 18:59:49 +02:00

Renamed from litex_boards/official/targets/ulx3s.py (Browse further)