Florent Kermarrec
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39d979a9d3
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targets/Ultrascale: add missing AsyncResetSynchronizer import.
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2020-11-09 10:25:05 +01:00 |
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Florent Kermarrec
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2b17dc1b89
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target: add rst signal to CRG to allow full reset of the SoC on reboot command.
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2020-11-04 11:13:42 +01:00 |
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Florent Kermarrec
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814e7630e4
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targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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2020-10-13 12:10:29 +02:00 |
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Florent Kermarrec
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c3ea04b6e9
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targets/s7/us: update sdram (manual cmd_latency no longer needed).
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2020-10-12 18:46:21 +02:00 |
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Florent Kermarrec
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1781be166a
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general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
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2020-08-23 15:00:17 +02:00 |
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Florent Kermarrec
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869ceadacb
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targets: use platform.request_all on LedChaser.
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2020-08-06 20:04:03 +02:00 |
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Florent Kermarrec
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7a48a61605
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targets: add indentifier on all targets.
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2020-06-30 18:11:04 +02:00 |
|
Florent Kermarrec
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eeba64d7b2
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targets: use soc.build_name in load/flash bitstream.
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2020-05-21 09:12:29 +02:00 |
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Florent Kermarrec
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6f22f082ff
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targets: add LedChaser on platforms with user_leds.
Default to Chaser mode and similar user interface than GPIOOut.
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2020-05-08 22:16:13 +02:00 |
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Florent Kermarrec
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da61aabc5b
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targets: remove USDDRPHY_DEBUG and set cmd_latency to on all Kintex7/Ultrascale targets.
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2020-05-05 16:32:10 +02:00 |
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Florent Kermarrec
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2d9543b65e
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targets: add build/load parameters on all targets.
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2020-05-05 15:11:47 +02:00 |
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Florent Kermarrec
|
4185a019f5
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targets: manual define of the SDRAM PHY is no longer needed.
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2020-04-16 11:25:59 +02:00 |
|
Florent Kermarrec
|
5f629c203b
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targets/vcu118: fix clk500 typo.
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2020-04-07 13:53:22 +02:00 |
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Florent Kermarrec
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3b91e96c42
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targets/add_constant: avoid specifying value when value is None (=default)
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2020-03-26 09:47:22 +01:00 |
|
Florent Kermarrec
|
555bf6c4dc
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targets/Ultrascale(+): enable USDDRPHY_DEBUG.
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2020-03-26 09:17:09 +01:00 |
|
Florent Kermarrec
|
83e6fb29f8
|
targets: switch to SoCCore/add_sdram instead of SoCSDRAM.
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2020-03-21 12:43:39 +01:00 |
|
Florent Kermarrec
|
74a5ffb9ef
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targets/Ultrascale+: use 500MHz IDELAYCTRL reference clock.
The minimum is 300MHz on Ultrascale+ vs 200MHz on Ultrascale.
|
2020-03-10 16:58:30 +01:00 |
|
Florent Kermarrec
|
e2a66090ee
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targets/Ultrascale(+): simplify CRG using USIDELAYCTRL.
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2020-03-10 16:55:22 +01:00 |
|
Florent Kermarrec
|
cf58550bba
|
targets/Ultrascale+: use USPDDRPHY.
|
2020-03-10 16:06:48 +01:00 |
|
Florent Kermarrec
|
f279fe9d33
|
vc707: cleanup platform/targets, remove Ethernet support (no Ethernet pads defined)
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2020-02-25 10:35:18 +01:00 |
|
Florent Kermarrec
|
88a1f80db1
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vc707/vcu118: use proper copyrights
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2020-02-25 09:03:52 +01:00 |
Fei Gao
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373e74f435
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add new board files for VC707 and VCU118, only specified limited ports for VCU118, including clock, reset and DDR4
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2020-02-24 14:20:47 -05:00 |