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150 Commits

Author SHA1 Message Date
Florent Kermarrec 7399d13cef paltforms/de10nano/sdram: enable fast input/output on dq. 2020-07-24 11:27:25 +02:00
Florent Kermarrec b4b1ab8621 paltforms/de10nano: simplify IO constraints (for consistency with others platforms). 2020-07-24 09:03:35 +02:00
enjoy-digital 89c5bf43cf
Merge pull request #92 from rob-ng15/master 
Enable use of HalfRateGENSDRPHY on de10nano
 2020-07-24 08:49:09 +02:00
Florent Kermarrec 1e1589a514 zybo_z7: demonstrate use of PS7 (with --cpu-type=zynq7000). 
This uses a pre-generated .xci hosted on github, still need to figure out where the best location for it.
 2020-07-23 17:45:21 +02:00
rob-ng15 cf9839307f
Add Misc 
Add Misc("") arguments to various inputs/outputs for stability. Allows de10nano to use HalfRateGENSDRPHY for sdram
 2020-07-23 14:40:04 +01:00
Florent Kermarrec 8a3b453e2f add Zybo Z7 minimal platform/targets: no PS7 support and USB-UART PMOD on JB. 2020-07-23 15:26:22 +02:00
Florent Kermarrec e723bef49a platforms/arty: add usb_uart_pmod_io (USB-UART PMOD on JA) to ease debug with a second UART (for UARTbone/LiteScope). 
Also use pmod connector names in i2s_pmod and sdcard_pmod.
 2020-07-22 14:41:09 +02:00
Florent Kermarrec 19d0b95867 platforms/targets: keep in sync with litex. 2020-07-22 08:53:49 +02:00
Florent Kermarrec 0ee4b215b9 trellisboard/ulx3s: fix sdcard slewrate. 2020-07-21 15:23:08 +02:00
Florent Kermarrec 7efa1c37a1 platforms/arty: add missing pullups on sdcard. 2020-07-21 15:22:39 +02:00
Florent Kermarrec 2ce24df76d platforms/genesys2: add internal_vref to 0.750v on bank 34 (DDR3). 2020-07-18 22:18:41 +02:00
Florent Kermarrec 135c387155 platforms/ulx3s: add assertion for supported devices. 2020-07-17 12:04:06 +02:00
Florent Kermarrec 851378f0a9 platforms/trellisboard: move ddram_vtt_en. 2020-07-17 12:03:37 +02:00
Vamsi K Vytla 44ad902aad platforms/kc705.py: LPC DP0_M2C/C2M diff pair 2020-07-13 10:26:17 -07:00
Greg Davill a461f5ac59 orangecrab: add usb, rst_n signals for r0.1 
- fix standard io extensions
 - Use newly assigned code for orangecrab 1209:5af0
 2020-07-09 19:56:32 +09:30
enjoy-digital f3d02d8fca
Merge pull request #87 from antmicro/arty_i2s 
arty: Add configuration of I2S pins
 2020-07-07 17:22:10 +02:00
Pawel Sagan df54b93db3 arty: Add configuration of I2S pins 2020-07-07 15:25:10 +02:00
Florent Kermarrec 40fbbbbebc platforms/orangecrab: add sdcard pins on r0_2. 2020-07-06 17:48:48 +02:00
enjoy-digital 49973990f3
Merge pull request #85 from oskirby/logicbone 
Add Logicbone ECP5 board
 2020-06-29 16:24:15 +02:00
Owen Kirby 76a32ba8ec Add Logicbone ECP5 board 
The Logicbone is an Open Source development board for the Lattice ECP5
being developed at https://github.com/oskirby/logicbone
 2020-06-27 03:32:47 -07:00
Florent Kermarrec 782c856619 platforms/genesys2: add usb_fifo. 2020-06-23 18:02:53 +02:00
Florent Kermarrec 936ba5b279 platforms/genesys2: add openocd specific configuration (channel 1 used for JTAG). 2020-06-23 11:55:50 +02:00
Florent Kermarrec 55ed9fbf02 platforms/kcu105: add sdcard/spisdcard. 2020-06-23 11:44:40 +02:00
Florent Kermarrec eee00ebd0a platforms/genesys2: add sdcard/spisdcard. 2020-06-23 11:44:26 +02:00
Florent Kermarrec 6568c8a3ae platforms/netv2: add spisdcard. 2020-06-23 11:44:10 +02:00
Florent Kermarrec 7de7c4be5c platforms/kc705: rename mmc to sdcard and make it similar to other boards. 2020-06-23 10:56:31 +02:00
Florent Kermarrec 0ecb8609b3 platform/arty: also update spisdcard. 2020-06-16 20:15:12 +02:00
Florent Kermarrec 7a8b0b743d platforms/pano_logic_g2: -x. 2020-06-16 19:53:46 +02:00
Kamil Rakoczy f70655d1ac Change sdcard Pmod from JB to JD 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-15 12:01:46 +02:00
Florent Kermarrec 04f6d4463a versa_ecp5: simplify device (LFE5UM5G or LFE5UM) and adapt integrated_rom_size only for Microwatt. 2020-06-13 11:17:05 +02:00
Raptor Engineering Development Team 90092164c8 Add device option for ECP5 Versa board 
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
 2020-06-12 18:39:43 -05:00
Florent Kermarrec 9b45ec0f35 de10lite: simplify vga terminal. 2020-06-11 19:59:32 +02:00
Florent Kermarrec 85cac7abc0 de10nano/Mister: review/simplify. 2020-06-11 19:54:55 +02:00
Florent Kermarrec c94cbae0c0 orangecrab: add user_led (RGB leds), DFUProg and --load support. 2020-06-11 19:21:40 +02:00
enjoy-digital 9aea2272eb
Merge pull request #80 from rob-ng15/master 
Use 128mb sdram, uart via i/o port on i/o board and vga terminal via i/o board
 2020-06-11 18:16:18 +02:00
enjoy-digital ad1693a1ad
Merge pull request #82 from Disasm/colorlight-5a-75e 
Add Colorlight 5A-75E V7.1 board
 2020-06-10 23:09:26 +02:00
enjoy-digital b312c65eb9
Merge pull request #81 from Disasm/fix-5a-75b 
Update J4 pin 5 on Colorlight 5A-75B V7.0
 2020-06-10 23:07:33 +02:00
Florent Kermarrec b6df166f5a platforms/arty: add spisdcard to _sdcard_pmod_io. 2020-06-10 17:38:16 +02:00
Florent Kermarrec 00c8e40d02 platforms/ulx3s: add sdcard pins. 2020-06-10 17:37:50 +02:00
Vadim Kaushan 1acdb962a5
Add 5A-75E V7.1 board 2020-06-10 03:07:20 +03:00
Vadim Kaushan 939f05fea4
Update J4 pin 5 on Colorlight 5A-75B V7.0 2020-06-10 02:49:18 +03:00
rob-ng15 e52d6aca5f
Use 128mb sdram, uart via i/o port on i/o board and vga terminal via i/o board 2020-06-08 11:05:36 +01:00
Florent Kermarrec 0b11aba8a1 platforms/nexys_video: add spisdcard pins. 2020-05-29 19:37:04 +02:00
enjoy-digital 33fe308ef0
Merge pull request #78 from antmicro/jboc/spd-read 
ZCU104: add I2C
 2020-05-27 14:56:31 +02:00
Jędrzej Boczar e5578a1ae8 zcu104/platform: change I2C number to 0 2020-05-27 14:31:22 +02:00
Jędrzej Boczar ac1f1cd6a7 zcu104: add I2C 2020-05-27 12:47:43 +02:00
Florent Kermarrec 2f3817cba9 pano_logic_g2: add ethernet (build but not functional yet) and use user_btn_n as sys_rst. 2020-05-27 10:13:12 +02:00
Florent Kermarrec f19bc36813 pano_logic_g2: add revision support (b and c, c as default) and add OpenOCD programmer. 
Tested with:
./pano_logic_g2.py --uart-name=jtag_uart --build --load
./litex_jtag_uart.py --config=openocd_xc6_ft232.cfg
lxterm /dev/pts/X
 2020-05-27 08:58:40 +02:00
Skip Hansen 0648c04158 Updated comment, added link to clocking documentation. 2020-05-25 14:48:24 -07:00
Skip Hansen 1ab46562bd Take Ethernet PHY out of reset so default clock is 125 Mhz (and baud rate is 115,200) 2020-05-25 10:11:03 -07:00