a611f035d6
targets: Move CRG before SoCCore init (More logical and simplify some specific reset schemes) and switch SoCCore to one line when possible.
...
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical.
Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
2022-04-21 12:19:45 +02:00
9d452b0d74
targets: Create target_group for target arguments.
2022-03-21 18:37:40 +01:00
cc8da9d341
targets: Simplify imports and switch to LiteXSocArgumentParser.
...
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
2022-03-21 16:59:40 +01:00
773444a7dd
targets: Switch to get_bios_filename/get_bitstream_filename.
2022-03-17 09:21:05 +01:00
4d45611935
targets: Replace JTAG Atlantic (Deprecated) with JTAG-UART.
2022-02-01 11:30:26 +01:00
9144cb44fb
Merge branch 'master' into jev/deca-eth
2022-01-31 16:22:58 +01:00
fbd424fc48
DECA: Add Ethernet and Etherbone support
...
Also fixed pcf_en IO standard compared to golden Arrow project.
2022-01-29 15:15:53 -08:00
9e5224ca49
Add JTAGbone support to Terasic DECA
...
Along the way I added UARTbone support to DECA as well for debugging.
Examples:
./terasic_deca.py --csr-csv csr.csv --with-jtagbone --build --load
litex_server --jtag --jtag-config ../prog/openocd_max10_blaster2.cfg
litex_term crossover
./terasic_deca.py --csr-csv csr.csv --uart-name jtag_uart --build --load
litex_term --jtag-config ../prog/openocd_max10_blaster2.cfg jtag
2022-01-27 14:13:58 -08:00
fccb952c4b
target: Remove ident_version=True no longer required.
2022-01-18 17:13:02 +01:00
53dc00eab7
targets/parser: Rely on argparse.ArgumentDefaultsHelpFormatter to provide default in help description.
...
Also do minor adjustments while doing this.
2022-01-05 17:06:40 +01:00
1920db3535
Add with_led_chaser argument to constructor of boards using LedChaser submodule.
2021-07-06 16:39:37 -05:00
7737575b88
terasic_deca: Remove --integrated-ram-size parameter (--integrated-main-ram-size provides the same functionnality).
2021-03-27 08:58:49 +01:00
f714e1210a
terasic_deca: Remove enforced CPU variant/debug: --cpu-variant=imac or --cpu-variant=imac+debug can be used for this.
...
The default CPU/Variant is defined in LiteX, enforcing the variant on the target
prevent usage of the other CPUs and also complicate maintenance.
2021-03-27 08:56:46 +01:00
53a767c85c
terasic_deca: Review/Cleanup for consistency with other boards.
2021-03-26 22:12:13 +01:00
8c0ddd140b
terasic_deca: fix cable name, ulpi, names, add gpio_serial
2021-03-26 10:46:37 +07:00
8a3cacae32
boards: Add Vendor prefix to platforms/targets name when useful and when multiple boards from the same vendor. (With Retro-Compat on the imports).
2021-03-25 14:11:17 +01:00
Florent Kermarrec
Jevin Sweval
Joey Bushagour
Hans Baier