ae6a052e57
alveo_u250: Add PCIe x4 support
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Based on the implementation in xcu1525
Signed-off-by: David Shah <dave@ds0.me>
2020-09-04 14:20:04 +01:00
2eda9d0252
xcu1525: add DDR4 IOs for C1/C2/C3 and fix compilation (untested).
2020-09-04 11:34:33 +02:00
7b6b71d4e3
xcu1525: add initial DDR4 support in C0 (untested).
2020-09-03 19:48:23 +02:00
5a62a07b45
xcu1525: add initial PCIe support (untested).
2020-09-03 19:26:02 +02:00
51e881d1ff
add minimal xcu1525 support (VCU1525 or BCU1525 boards).
2020-09-03 19:06:43 +02:00
8bd736bd77
targets/colorlight_5a_75x: make Ethernet PHY selectable, cast sys_clk_freq to int for Wishbone
2020-09-02 22:08:45 +02:00
cc78574297
targets/colorlight_5a_75x: fix rx_data pin order for Ethernet PHY 0
2020-09-02 22:04:23 +02:00
24b853c2db
targets/colorlight_5a_75x: force use of internal oscillator when using Ethernet with 5A-75E V6.0
2020-09-01 17:07:52 +02:00
8b1fee0e66
Add support for 5A-75E V6.0 board
2020-09-01 17:02:17 +02:00
9b6ed6bdf1
targets/orangecrab: add fallback to bootloader when usr_btn is pressed for 1 second.
2020-09-01 16:22:32 +02:00
b9ac72cf78
targets: simplify clocking on iCE40/ECP5 targets (AsyncResetSynchronizer now integrated in PLL).
2020-09-01 13:38:32 +02:00
9e2d301745
targets/icebreaker: simplify, update PLL/API and BIOS execution from SPI Flash.
2020-09-01 12:58:13 +02:00
beccecf59f
orangecrab: reduce DDR3 power consumption/heat and get back USB PLL to CRGSDRAM.
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- disable DQ termination.
- disable RTT_NOM.
- drive VCCIO/GND pads.
Reduce current from 0.25A to 0.12A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=48e6.
Still working at 96MHz, 0.17A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=96e6.
See https://github.com/enjoy-digital/litedram/issues/216 .
2020-08-28 20:01:54 +02:00
63b65e278c
crosslink_nx_evn: update copyrights.
2020-08-24 22:33:58 +02:00
153326fa26
targets/icebreaker: update flash.
2020-08-24 17:19:15 +02:00
795e34aafd
add initial Crosslink-NX support.
2020-08-24 16:47:38 +02:00
84c19a6cdf
targets/de0nano: set sys2x_ps phase to 180° for sdram_rate=1:2.
2020-08-24 09:28:51 +02:00
70594a5305
ulx3s: simplify sdram constraints and increase phase to 180 for sdram_rate=1:2.
2020-08-24 09:05:58 +02:00
1781be166a
general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
2020-08-23 15:00:17 +02:00
83d8b8d1b4
platforms/acorn_cle_215: integrated sdcard ios as extension.
2020-08-22 22:11:51 +02:00
d365836af5
Merge pull request #100 from connorwk/master
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Changes to acorn-cle-215 platform/target files.
2020-08-22 22:04:52 +02:00
f328909578
Moved platform call inside of BaseSoC init for compatibility with linux-on-litex-vexriscv support. Added optional spi-sdcard support over P2 header.
2020-08-09 16:27:41 -04:00
45bb329b56
targets/colorlight_5a_75x: enable HalfRate SDRAM PHY.
2020-08-07 19:26:12 +02:00
b6a1ad5a9c
targets/orangecrab: add simple CRG when built without DDR3.
2020-08-07 18:10:03 +02:00
869ceadacb
targets: use platform.request_all on LedChaser.
2020-08-06 20:04:03 +02:00
8583c44063
Merge pull request #98 from antmicro/arty_pmod_configuration
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arty: Change USB-uart and I2S Pmod configuration
2020-08-05 12:30:10 +02:00
d2cd6d4c0e
arty: Change USB-uart and I2S Pmod configuration
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This makes it compatible with the Arty A7 expansion board by Antmicro
(https://github.com/antmicro/arty-expansion-board ).
2020-08-05 11:54:25 +02:00
ee28d7b5ec
targets/ulx3s/add_oled: simplify.
2020-08-04 12:31:15 +02:00
623faa9d24
Merge pull request #96 from pepijndevos/oled
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Add optional OLED peripheral to ULX3S target
2020-08-04 12:19:58 +02:00
eba70377b7
add optional OLED peripheral to ULX3S target
2020-08-04 11:07:30 +02:00
929e55d7e6
platforms/trellisboard: add SDCard PMOD pins.
2020-07-29 09:07:55 +02:00
5fd3e8dbcd
ecpix5: add SDCard.
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Validated with Linux-on-LiteX-VexRiscv.
2020-07-28 17:45:49 +02:00
f0581815f5
README: fix typo.
2020-07-28 17:44:30 +02:00
94ccf1dd3e
targets/trellisboard: simplify clocking when no DDR3, remove firmware_ram (was here for debug).
2020-07-27 16:31:46 +02:00
ecdc1ef7fd
README: add missings .
2020-07-27 11:44:30 +02:00
361afa74b6
README: add links to LiteX's wiki.
2020-07-27 11:05:14 +02:00
02c0c0a1b1
README: add board picture and fix a few typos.
2020-07-27 08:53:12 +02:00
eb8a484032
targets/de10nano: fix typo.
2020-07-26 12:01:11 +02:00
2cef54a909
targets/colorlight_5a_75x: avoid sys_clk_freq of 125MHz with etherbone (no longer required).
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This allows creating SoCs with CPU, SDRAM and Etherbone enabled all together.
2020-07-26 11:58:42 +02:00
bfbee484c7
Readme/boards: fill most of the missing infos.
2020-07-25 22:17:22 +02:00
bb65692590
add LICENSE.
2020-07-25 20:23:52 +02:00
e9706d4465
README: add initial contents and list of supported boards.
2020-07-25 20:21:51 +02:00
760b8ff93a
arty: improve xy_pmod_io genericity (allow selecting the PMOD) and enable SDCard.
2020-07-24 16:29:35 +02:00
04fc98f834
de0nano/ulx3s: add sdram HalfRate support (untested).
2020-07-24 16:12:46 +02:00
d0ca1befa6
targets/de10nano/minispartan6: simplify HalfRate support, rename argument to sdram_rate.
2020-07-24 16:11:57 +02:00
9730c6f722
platforms/de10nano: use additional sdram constraints required for HalfRate.
2020-07-24 12:27:36 +02:00
7399d13cef
paltforms/de10nano/sdram: enable fast input/output on dq.
2020-07-24 11:27:25 +02:00
b4b1ab8621
paltforms/de10nano: simplify IO constraints (for consistency with others platforms).
2020-07-24 09:03:35 +02:00
89c5bf43cf
Merge pull request #92 from rob-ng15/master
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Enable use of HalfRateGENSDRPHY on de10nano
2020-07-24 08:49:09 +02:00
1e1589a514
zybo_z7: demonstrate use of PS7 (with --cpu-type=zynq7000).
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This uses a pre-generated .xci hosted on github, still need to figure out where the best location for it.
2020-07-23 17:45:21 +02:00
David Shah
Florent Kermarrec
DerFetzer
Piense
connorwk
Pawel Sagan
Pepijn de Vos