eadea43fa1
honours lattice toolchain args
2022-06-22 21:05:35 +02:00
45494f60e0
targets: Change SoC/Software headers generation behaviour (Now only generated with --build).
...
Re-generating the SoC/Software headers was causing some un-expected behaviours for users not familiar
with the flow. For example doing a --load with a different configuration, was re-generating the Software
headers and messing up things when trying to run software on the SoC.
2022-05-06 15:14:32 +02:00
877bc4b45e
targets: Use full imports (vendor_board).
2022-05-02 12:55:11 +02:00
353aba0359
targets: Move USB-ACM/ValentyUSB clone directly to LiteX to avoid duplication in targets.
2022-04-21 15:43:50 +02:00
a611f035d6
targets: Move CRG before SoCCore init (More logical and simplify some specific reset schemes) and switch SoCCore to one line when possible.
...
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical.
Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
2022-04-21 12:19:45 +02:00
00ff61baa9
targets: Simplify clock domains and remove useless reset_less.
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rst was not directly assigned/used on reset_less clock domains, so reset_less
property was not really useful. With the changes on stream.CDC, having a rst
(Even fixed at 0) is now mandatory on clock domains involved in the CDC, so this
also fixes targets.
2022-04-01 11:30:38 +02:00
9d452b0d74
targets: Create target_group for target arguments.
2022-03-21 18:37:40 +01:00
cc8da9d341
targets: Simplify imports and switch to LiteXSocArgumentParser.
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CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
2022-03-21 16:59:40 +01:00
fccb952c4b
target: Remove ident_version=True no longer required.
2022-01-18 17:13:02 +01:00
4b6a9b2cf0
targets/spiflash: Simplify self.cpu.set_reset_address call.
2022-01-07 15:19:23 +01:00
8151bf7ffa
targets: Update and simplify SPI-Flash support (Address is now automatically allocated).
2022-01-07 10:34:47 +01:00
53dc00eab7
targets/parser: Rely on argparse.ArgumentDefaultsHelpFormatter to provide default in help description.
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Also do minor adjustments while doing this.
2022-01-05 17:06:40 +01:00
8664b59f23
targets: Fix --bios-flash-offset support and other minor cleanups.
2021-12-20 21:41:12 +01:00
82653cf66f
icebreaker/fomu: Fix SPRAM split.
2021-09-30 09:32:26 +02:00
5addd7f7d8
icebreaker/fomu: Split PSRAM in half: 64kB SRAM/64kB RAM).
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Allows building bare metal demo and running it directly on these boards.
2021-09-29 19:33:22 +02:00
35ba3d9bc3
targets: Remove old call to add_spi_flash on targets now using LiteSPI (we'll find it with gitk is required).
2021-07-29 11:55:10 +02:00
54cee05986
#248 : Minor cleanup.
2021-07-28 18:20:42 +02:00
7b3dce65c1
Add option for different Fomu SPI chips.
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Signed-off-by: Joey Bushagour <jbushagour@google.com>
2021-07-28 10:34:02 -05:00
fa3cc9b753
kosagi_fomu/spiflash: Switch to READ_1_1_4.
2021-07-28 11:10:34 +02:00
9065cfa75d
kosagi_fomu: Switch to LiteSPI.
2021-07-27 19:55:04 +02:00
55ba0591df
targets: Remove SpiFlash imports (Obsolete since integration is provided by LiteX).
2021-07-27 19:35:19 +02:00
a455713e0c
kosagi_fomu: Handle bios_flash_offset in flash function and make DFU flash offset explicit.
2021-07-21 11:41:35 +02:00
1920db3535
Add with_led_chaser argument to constructor of boards using LedChaser submodule.
2021-07-06 16:39:37 -05:00
bf123db20b
icebreaker/fomu: Update flashing and disconnect reset from SoC (will need proper support in iCE40PLL).
2021-05-20 09:14:54 +02:00
8a3cacae32
boards: Add Vendor prefix to platforms/targets name when useful and when multiple boards from the same vendor. (With Retro-Compat on the imports).
2021-03-25 14:11:17 +01:00
Gwenhael Goavec-Merou
Florent Kermarrec
Joey Bushagour