4a18951651
tul_pynq_z2: Fix copyrights, remove PS7 part for now.
2021-09-01 08:50:56 +02:00
54c777a49c
Merge pull request #252 from developandplay/PYNQ-Z2
...
WIP: Initial PYNQ Z2 support
2021-09-01 08:46:44 +02:00
6a08a7973c
Merge pull request #251 from niw/fix_orangecrab_feather_spi_pad_name
...
FIX: OrangeCrab Feather SPI pad name
2021-08-31 18:59:09 +02:00
8f1c15bdb8
ebaz4205: Remove PS7 support for now (since untested and we'll avoid the .xci in LiteX-Boards repository).
2021-08-31 18:56:47 +02:00
781d83bab6
Add support for EBAZ4205 'Development' Board
...
Usage:
```
./ebaz4205.py --cpu-type=vexriscv --build --load
```
```
$ pwd
litex-boards/litex_boards/targets
```
Tip: Use `GTKTerm` to connect to /dev/ttyUSB0 (usually) and interact
with the LiteX BIOS.
References:
- https://github.com/fusesoc/blinky#ebaz4205-development-board
- https://github.com/olofk/serv/#ebaz4205-development-board
- https://github.com/xjtuecho/EBAZ4205#ebaz4205
- https://github.com/nmigen/nmigen-boards/pull/180 (merged)
- https://github.com/olofk/corescore/pull/33
- The existing 'Zybo Z7' example
Note: The `PS7` stuff remains untested via LiteX for now.
2021-08-31 18:54:49 +02:00
fc78c96444
FIX: OrangeCrab Feather SPI pad name
...
**Problems**
`SPIMaster` pad names are `clk`, `cs_n`, `mosi`, and `miso`.
However, `feather_spi` is using `sck` instead of `clk`, therefore
it is not able to use as-is for `SPIMaster`, for example,
with `add_spi` on Linux On LiteX VexRiscv.
**Solution**
In fact, `spisdcard` and other SPI related pad names are
using `clk`, only `feather_spi` is using `sck`.
Therefore, rename `sck` to `clk`.
2021-08-29 17:59:45 -07:00
b017a33f2b
targets: Fix SPI Flash mapping on target supporting --with-spi-flash.
2021-08-23 18:05:40 +02:00
cc9e39286a
lattice_crosslink_nx_evn: allow specifying the FPGA device
...
This board is documented as having the LIFCL-40-9BG400C part, but some
versions of the board exist which were fitted with LIFCL-40-8BG400CES,
an engineering sample part. The distinction is important because the
engineering sample requires a different device ID to be embedded in the
bitstream. If you try to build a bitstream for LIFCL-40-9BG400C and load
it onto LIFCL-40-8BG400CES the configuration fails (indicated by the red
"INITN" LED on this board).
Accept --device to allow the user to specify which FPGA part their board
has.
2021-08-17 18:30:03 +10:00
f1e1ae2f71
Merge pull request #256 from alainlou/master
...
update IRC channel in README
2021-08-16 11:53:37 -07:00
126c98488a
update IRC channel
2021-08-16 14:18:08 -04:00
db9c98b28a
beaglewire platform and target added
2021-08-16 20:14:45 +05:30
22e823d756
Initial PYNQ Z2 support
2021-08-13 16:23:39 +02:00
b77b1514ce
Merge pull request #250 from david-sawatzke/fullmemwe
...
colorlight_5a_75x: Disable full_memory_we for l2 cache by default
2021-08-11 09:53:47 +02:00
9f5e8d4864
colorlight_5a_75x: Disable full_memory_we for l2 cache by default
...
Leads to an increase in DP16KD, first noticed in
https://github.com/enjoy-digital/liteeth/issues/70 .
With full_mem_we:
```
Info: DP16KD: 41/ 56 73%
```
Without:
```
Info: DP16KD: 29/ 56 51%
```
2021-08-08 14:37:46 +02:00
b81309401e
Initial Digilent Atlys support
2021-08-06 13:24:19 +02:00
615b97e205
tinyfpga_bx: Switch to LiteSPI.
2021-07-30 08:18:15 +02:00
90fcaec287
targets/radiona_ulx3s: Switch to LiteSPI.
2021-07-30 08:10:52 +02:00
fdf94b95c9
muselabe_icesugar/SPIFlash: Disable Master (to avoid wasting resources on this small FPGA).
2021-07-29 19:59:22 +02:00
218e830fbf
muselab_icesugar_pro: Switch to LiteSPI.
2021-07-29 19:58:13 +02:00
569c20ab86
muselab_icesugar: Switch to LiteSPI.
2021-07-29 19:55:32 +02:00
8df797c716
lattice_ice40up5k_evn: Switch to LiteSPI.
2021-07-29 19:50:36 +02:00
5e8c29d657
colorlight_i5: Switch to LiteSPI.
2021-07-29 19:47:41 +02:00
35ba3d9bc3
targets: Remove old call to add_spi_flash on targets now using LiteSPI (we'll find it with gitk is required).
2021-07-29 11:55:10 +02:00
54cee05986
#248 : Minor cleanup.
2021-07-28 18:20:42 +02:00
a41fbea5e6
Merge pull request #248 from JosephBushagour/jbushagour_fomu_spi_options
...
Add option for different Fomu SPI ICs.
2021-07-28 18:18:12 +02:00
99ff82c75a
xilinx_alveo_u280: Add more IOs and enable HBM2.
2021-07-28 18:11:49 +02:00
7b3dce65c1
Add option for different Fomu SPI chips.
...
Signed-off-by: Joey Bushagour <jbushagour@google.com>
2021-07-28 10:34:02 -05:00
401568c54e
digilent_arty_s7: Add SPI Flash.
2021-07-28 14:22:26 +02:00
64eadd8012
hackaday_hadbadge: Lower PLL's PFD Min from 10MHz to 8MHz.
...
This is now required since ECP5PLL now checks that PFD is in required range.
2021-07-28 12:25:17 +02:00
6ce5db1b90
qmtech_xc7a35t: Fix default build.
2021-07-28 12:23:24 +02:00
1f4383475a
decklink_intensity_pro_4k: Fix default build.
2021-07-28 12:23:12 +02:00
2f3c886280
test/test_targets: Rename test_simple to test_platforms and add test_targets.
2021-07-28 12:13:40 +02:00
f080764c88
test_targets: Collect platforms automatically.
2021-07-28 12:03:37 +02:00
3e8b6677e9
platforms: Make sure all platforms have a default Clk. (To be able to run simple target).
2021-07-28 12:03:06 +02:00
4e2b596ab3
digilent_arty/qmtech_xc7a35t: Rename --with-mapped-flash to --with-spi-flash.
2021-07-28 11:21:51 +02:00
fa3cc9b753
kosagi_fomu/spiflash: Switch to READ_1_1_4.
2021-07-28 11:10:34 +02:00
1118b09350
trenz_tec0117: Switch to LiteSPI.
2021-07-28 10:34:17 +02:00
9065cfa75d
kosagi_fomu: Switch to LiteSPI.
2021-07-27 19:55:04 +02:00
b3e7dbfd30
qmtech_xc7a35t: LiteSPI integration now provided by LiteX.
2021-07-27 19:39:50 +02:00
55ba0591df
targets: Remove SpiFlash imports (Obsolete since integration is provided by LiteX).
2021-07-27 19:35:19 +02:00
1c52e6b8fb
targets/digilent_arty/spiflash: LiteSPI integration now provided by LiteX.
2021-07-27 19:30:38 +02:00
15b5aec23f
1bitsquared_icebreaker_bitsy: Also switch to LiteSPI.
2021-07-27 19:27:28 +02:00
959780f372
1bitsquared_icebreaker: Switch to LiteSPI (with integration now done by LiteX).
...
Keep the old add_spi_flash call commented for now just in case we need to compare/test it.
2021-07-27 19:23:26 +02:00
533d25e845
1bitsquared_icebreaker: Enable LiteSPI Master but reduce FIFO depth to reduce resource usage.
...
Already better regarding resource usage:
Info: ICESTORM_LC: 2938/ 5280 55%
Info: ICESTORM_RAM: 2/ 30 6%
Info: SB_IO: 15/ 96 15%
Info: SB_GB: 8/ 8 100%
Info: ICESTORM_PLL: 1/ 1 100%
Info: SB_WARMBOOT: 0/ 1 0%
Info: ICESTORM_DSP: 0/ 8 0%
Info: ICESTORM_HFOSC: 0/ 1 0%
Info: ICESTORM_LFOSC: 0/ 1 0%
Info: SB_I2C: 0/ 2 0%
Info: SB_SPI: 0/ 2 0%
Info: IO_I3C: 0/ 2 0%
Info: SB_LEDDA_IP: 0/ 1 0%
Info: SB_RGBA_DRV: 0/ 1 0%
Info: ICESTORM_SPRAM: 4/ 4 100%
2021-07-27 17:38:25 +02:00
12fb315e09
1bitsquared_icebreaker: Disable LiteSPI Master.
...
Requires 80e9d2cea9
2021-07-27 17:00:55 +02:00
0f648ac4ef
1bitsquared_icebreaker: Add test code to use LiteSPI.
...
Both XiP from SPI(1X) or QSPI(4X) are working, but resource usage is currently
too high to be able to switch to it by default. We'll first try to reduce it.
Resource usage using SPI(1X) and actual LiteX SPI Flash core:
Info: Device utilisation:
Info: ICESTORM_LC: 2016/ 5280 38%
Info: ICESTORM_RAM: 2/ 30 6%
Info: SB_IO: 15/ 96 15%
Info: SB_GB: 8/ 8 100%
Info: ICESTORM_PLL: 1/ 1 100%
Info: SB_WARMBOOT: 0/ 1 0%
Info: ICESTORM_DSP: 0/ 8 0%
Info: ICESTORM_HFOSC: 0/ 1 0%
Info: ICESTORM_LFOSC: 0/ 1 0%
Info: SB_I2C: 0/ 2 0%
Info: SB_SPI: 0/ 2 0%
Info: IO_I3C: 0/ 2 0%
Info: SB_LEDDA_IP: 0/ 1 0%
Info: SB_RGBA_DRV: 0/ 1 0%
Info: ICESTORM_SPRAM: 4/ 4 100%
Resource usage using LiteSPI:
Info: Device utilisation:
Info: ICESTORM_LC: 3964/ 5280 75%
Info: ICESTORM_RAM: 2/ 30 6%
Info: SB_IO: 15/ 96 15%
Info: SB_GB: 8/ 8 100%
Info: ICESTORM_PLL: 1/ 1 100%
Info: SB_WARMBOOT: 0/ 1 0%
Info: ICESTORM_DSP: 0/ 8 0%
Info: ICESTORM_HFOSC: 0/ 1 0%
Info: ICESTORM_LFOSC: 0/ 1 0%
Info: SB_I2C: 0/ 2 0%
Info: SB_SPI: 0/ 2 0%
Info: IO_I3C: 0/ 2 0%
Info: SB_LEDDA_IP: 0/ 1 0%
Info: SB_RGBA_DRV: 0/ 1 0%
Info: ICESTORM_SPRAM: 4/ 4 100%
2021-07-27 16:50:18 +02:00
0ca203487b
pr243: Make led_chaser optional.
2021-07-27 15:00:18 +02:00
9835bd5f93
targets/muselab_icesugar_pro: +x.
2021-07-27 14:56:33 +02:00
2df3f9e664
pr243/platforms: Consistency with other platforms.
2021-07-27 14:55:19 +02:00
3fb73b3603
platforms/digilent_nexys4ddr: Fix INTERNAL_VREF voltage (0.900v instead of 0.750v).
2021-07-27 12:29:42 +02:00
Florent Kermarrec
Dhiru Kholia
Yoshimasa Niwa
Dan Callaghan
Tim Ansell
alainlou
ombhilare999
Martin Troiber
David Sawatzke
MV
Sergiu Mosanu
Joey Bushagour