9a7e5f40b4
efinix_trion_t120_bga576_dev_kit: Add Ethernet/Etherbone support.
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Still not fully validated: TX seems OK but RX seems shifted/corrupted.
2021-11-09 11:32:32 +01:00
ccebae6f55
targets/hyperram: Update integration.
2021-11-08 16:39:49 +01:00
184f41e61a
sipeed_tang_nano: Use PLL and 48MHz sys_clk, switch to SoCMini, add UARTBone (at 1MBauds).
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Working correctly on hardware with updated CH552 firmware & patched litex_server...
2021-11-08 09:23:44 +01:00
63913d8c82
Merge pull request #292 from hansfbaier/master
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terasic_sockit now also can use the DRAM module from litedram
2021-11-08 08:05:54 +01:00
8124c51dd0
Merge branch 'litex-hub:master' into master
2021-11-08 12:48:23 +07:00
d6bf2fd00e
terasic_sockit: Use standard SDRAM module from litedram
2021-11-08 12:48:03 +07:00
91d0cd50ea
Merge pull request #291 from sergachev/master
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sqrl_acorn: add vivado programmer option, fix warnings
2021-11-07 22:14:11 +01:00
099d947a49
sqrl_acorn: fix vivado cfgbvs and config_voltage warnings
2021-11-07 16:18:22 +01:00
202b0e3e7d
sqrl_acorn: add option to use vivado programmer
2021-11-07 16:18:00 +01:00
3dbad2ee06
Merge pull request #289 from hansfbaier/qmtech-altera-fixes
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QMTech Altera fixes
2021-11-06 08:34:34 +01:00
f0356d8434
QMTech Daughterboard: remove xilinx specific attribute
2021-11-06 10:25:57 +07:00
a9847f15a7
qmtech_5cefa2: tuned the clock phase shift to be able to run the system at 105MHz
2021-11-06 09:58:10 +07:00
b2813cfb70
use the right DRAM chip for the QMTech Altera boards
2021-11-06 08:45:03 +07:00
ee5638a96b
qmtech-boards: fix serial so that it gets replaced by daughterboard serial correctly
2021-11-06 06:49:25 +07:00
6e7c76b71e
fairwaves_xtrx: Add clk60 (from USB PHY) as default Clk when no PCIe.
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Fixes CI.
2021-11-05 15:22:55 +01:00
ce229d60fb
Merge pull request #288 from litex-hub/fairwaves_xtrx
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Add initial Fairwaves XTRX support (SoC with JTAG-UART and PCIe Gen2 X1).
2021-11-05 14:53:42 +01:00
ceaaf67dfd
Add initial Fairwaves XTRX support (SoC with JTAG-UART and PCIe Gen2 X1).
2021-11-05 14:52:45 +01:00
01463a81a4
Merge pull request #287 from hansfbaier/qmtech-fixes
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10cl006: add missing spiflash option
2021-11-05 07:11:27 +01:00
4d99073ce3
Merge pull request #286 from hansfbaier/qmtech-5cefa2
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Add support for QMTech 5CEFA2 board (Cyclone V)
2021-11-05 07:11:04 +01:00
3a25af1c28
10cl006: add missing spiflash option
2021-11-05 09:57:04 +07:00
0edce3a176
Add support for QMTech 5CEFA2 board (Cyclone V)
2021-11-05 09:53:25 +07:00
a482d7f6de
targets/qmtech_xc7a35t: Use gpio_serial as serial when not mounted on daughterboard.
2021-11-04 18:52:36 +01:00
9543b5efae
marble/marble_mini: Add berkeleylab prefix.
2021-11-04 18:42:16 +01:00
5e5ae880a4
targets/litex_acorn_baseboard: Integrate WS2812/NeoPixel.
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Tested with:
./litex_acorn_baseboard.py --cpu-type=None --uart-name=uartbone --with-ws2812 --build --csr-csv=csr.csv --load
litex_server --uart --uart-port=/dev/ttyUSBX
And test script: https://gist.github.com/enjoy-digital/c32c679a9ee4429d7f38a5ca5016a45a
2021-11-04 16:36:25 +01:00
808befec3b
Merge pull request #283 from yetifrisstlama/master
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add Marble-board platform and target file
2021-11-04 15:20:11 +01:00
a4f8f12067
Merge pull request #284 from hansfbaier/master
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QMTech boards: fix swapped RX/TX lines, remove double uart replacer
2021-11-04 15:18:16 +01:00
2c2a6fe459
Merge pull request #285 from lapnd/master
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Use built-int RS232 port
2021-11-04 15:17:30 +01:00
d950b3feb5
Use built-int RS232 port
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Signed-off-by: lapd <lapd@soc.one>
2021-11-03 22:50:40 +07:00
7aa639ac0f
QMTech boards: fix swapped RX/TX lines, remove double uart replacer
2021-11-02 09:34:25 +07:00
e645eb243b
add marble board platform and target file
2021-10-28 18:41:22 +02:00
0c3f5b0fe1
prog/openocd_butterstick: Set _CHIPNAME to ecp5 (for jtag_uart/jtag_bone).
2021-10-27 17:27:07 +02:00
207afb98fc
ego1: Switch to VideoTerminal (LiteVideo is no longer provided by default with LiteX).
2021-10-27 16:29:46 +02:00
91818bc5f0
targets/gsd_butterstick/BaseSoC: Set default device to 85F (consistency with default arguments).
2021-10-26 17:01:55 +02:00
c7a91f9eab
efinix: Enable identifier on SoC (issue fixed in LiteX).
2021-10-25 19:33:49 +02:00
4bcfde8882
efinix: Avoid no_we on ROM/RAMs (no longer required).
2021-10-25 19:10:03 +02:00
d13a8d54b8
efinix_trion_txy_dev_kit: Lower sys_clk_freq for now to 50MHz, enable QSPI on T120 BGA576 dev kit.
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Now possible with recent LiteX changes to support Tristate IOs.
2021-10-25 18:35:35 +02:00
f230eaf9bc
efinix_trion_t120_bga576: Add Tristate test code.
2021-10-25 15:01:34 +02:00
0ac0f9e75d
efinix_xyloni_dev_kit: Switch to openFPGALoader to load bitstream.
2021-10-25 12:49:48 +02:00
fc05379929
efinix_xyloni_dev_kit: Use PLL.
2021-10-25 12:16:47 +02:00
16a629269d
efinix_xyloni_dev_kit: Describe IOs in similar order than the other platforms.
2021-10-22 14:52:38 +02:00
394ea23b99
efinix_xyloni_dev_kit: Only force variant to minimal for Vexriscv.
2021-10-22 14:47:12 +02:00
75fd276dbe
efinix_xyloni_dev_kit: Increase similarities with others boards and make target very similar to iceBreaker/Fomu/TangNano4k.
2021-10-21 11:34:55 +02:00
dc1328f1a5
efinix_xyloni_dev_kit: Fix copyrights.
2021-10-21 10:12:46 +02:00
012c1d9705
efinix_trion_t20: Minor changes (move serial to platform, fix platform copyright).
2021-10-21 10:10:35 +02:00
0cf9793be5
Merge pull request #282 from AndrewD/master
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efinix: xyloni dev board basic support
2021-10-21 10:06:25 +02:00
7525132907
litex_acorn_baseboard/video: Switch to 800x600@60Hz.
2021-10-19 16:34:28 +02:00
c548b1c1e2
efinix: xyloni dev board basic support
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* This works: efinix_xyloni_dev_kit.py --cpu-type None --build --load --flash
* issues with SPIflash - wrong generation for tristates miso mosi for
some reason
2021-10-19 11:23:29 +11:00
a53f17380f
Merge pull request #271 from antmicro/add-data-center-board
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WIP: boards: added datacenter DDR4 RDIMM tester board
2021-10-18 13:36:37 +02:00
a2261a1e9a
Merge pull request #280 from developandplay/master
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Fix tang nano loopback and button
2021-10-16 09:09:39 +02:00
5c716511d8
Merge pull request #281 from trabucayre/efinix_timing_model
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efinix_trion_xx: append device with timing model
2021-10-16 08:48:40 +02:00
Florent Kermarrec
Hans Baier
Ilia Sergachev
lapd
Michael Betz
Andrew Dennison