Stafford Horne 52ce49cf0c arty: Add an option to enable jtagbone ... Then adds jtagbone for arty. I have tested with the following litex_server and it seems to work fine. litex_server --jtag --jtag-config openocd_xc7_ft2232.cfg Note, the jtagbone and etherbone may be mutually exclusive, but I am not sure how to define that in the args.		2021-03-08 07:05:54 +09:00
..
__init__.py
ac701.py
acorn_cle_215.py
aller.py
alveo_u250.py	targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).	2021-03-04 19:49:03 +01:00
arrow_sockit.py	sockit: Add an option to plug in an UART via the GPIO daughter board	2021-02-10 14:52:19 +07:00
arty.py	arty: Add an option to enable jtagbone	2021-03-08 07:05:54 +09:00
arty_s7.py
c10lprefkit.py
camlink_4k.py
colorlight_5a_75x.py
colorlight_i5.py
crosslink_nx_evn.py
crosslink_nx_vip.py
de0nano.py
de1soc.py
de2_115.py
de10lite.py	platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support.	2021-03-03 18:05:24 +01:00
de10nano.py	platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support.	2021-03-03 18:05:24 +01:00
deca.py	platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support.	2021-03-03 18:05:24 +01:00
ecp5_evn.py
ecpix5.py
fk33.py
fomu.py
fpc_iii.py
genesys2.py
hadbadge.py
icebreaker.py	targets/video: Simplify/Cleanup integration.	2021-03-05 14:40:27 +01:00
kc705.py
kcu105.py	targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).	2021-03-04 19:49:03 +01:00
kx2.py
linsn_rv901t.py
litefury.py
logicbone.py
mercury_xu5.py	targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).	2021-03-04 19:49:03 +01:00
mimas_a7.py
minispartan6.py
mist.py	platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support.	2021-03-03 18:05:24 +01:00
nereid.py
netv2.py
nexys4ddr.py	targets/video: Simplify/Cleanup integration.	2021-03-05 14:40:27 +01:00
nexys_video.py	targets/video: Simplify/Cleanup integration.	2021-03-05 14:40:27 +01:00
orangecrab.py
pano_logic_g2.py
pipistrello.py
qmtech_ep4ce15.py
qmtech_wukong.py
redpitaya.py
sds1104xe.py	targets/sds1104xe: Enable both Ethernet/Etherbone with hybrid LiteEthMAC.	2021-02-23 15:27:50 +01:00
simple.py
tagus.py
tec0117.py
tinyfpga_bx.py
trellisboard.py
ulx3s.py
vc707.py
vcu118.py	targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).	2021-03-04 19:49:03 +01:00
versa_ecp5.py
xcu1525.py	targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).	2021-03-04 19:49:03 +01:00
zcu104.py	targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).	2021-03-04 19:49:03 +01:00
ztex213.py
zybo_z7.py