| .. |
|
__init__.py
|
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
|
2020-02-03 09:36:30 +01:00 |
|
ac701.py
|
targets/ac701: rename --ethernet-phy to --eth-phy for consistency with others targets.
|
2021-01-08 18:50:01 +01:00 |
|
acorn_cle_215.py
|
Be friendlier about incompatible options.
|
2021-01-29 18:08:38 -07:00 |
|
aller.py
|
targets/xilinx: add comment on sys_clk to pll.clkin false path.
|
2021-01-07 08:01:54 +01:00 |
|
alveo_u250.py
|
targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).
|
2021-03-04 19:49:03 +01:00 |
|
arrow_sockit.py
|
sockit: Add an option to plug in an UART via the GPIO daughter board
|
2021-02-10 14:52:19 +07:00 |
|
arty.py
|
arty: Add an option to enable jtagbone
|
2021-03-08 07:05:54 +09:00 |
|
arty_s7.py
|
targets/xilinx: add comment on sys_clk to pll.clkin false path.
|
2021-01-07 08:01:54 +01:00 |
|
c10lprefkit.py
|
targets/c10lprefkit: fix default sys-clk-freq.
|
2021-01-12 16:15:52 +01:00 |
|
camlink_4k.py
|
camlink_4k: disable leds when serial is used (since pin is shared).
|
2021-01-25 12:19:29 +01:00 |
|
colorlight_5a_75x.py
|
Be friendlier about incompatible options.
|
2021-01-29 18:08:38 -07:00 |
|
colorlight_i5.py
|
targets/colorlight_i5: use .bit stream instead of .svf when loading.
|
2021-02-03 08:17:24 +09:00 |
|
crosslink_nx_evn.py
|
nexus: Allow selection of toolchain
|
2020-11-25 09:45:25 +00:00 |
|
crosslink_nx_vip.py
|
nexus: Allow selection of toolchain
|
2020-11-25 09:45:25 +00:00 |
|
de0nano.py
|
targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
|
2021-01-04 11:38:07 +01:00 |
|
de1soc.py
|
targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
|
2021-01-04 11:38:07 +01:00 |
|
de2_115.py
|
targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
|
2021-01-04 11:38:07 +01:00 |
|
de10lite.py
|
platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support.
|
2021-03-03 18:05:24 +01:00 |
|
de10nano.py
|
platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support.
|
2021-03-03 18:05:24 +01:00 |
|
deca.py
|
deca: Integrate Video Terminal (untested, resource issue).
|
2021-03-09 15:02:30 +01:00 |
|
ecp5_evn.py
|
targets: cleanup, uniformize build arguments between targets.
|
2020-11-12 11:46:00 +01:00 |
|
ecpix5.py
|
ecpix5: Add Etherbone (--with-etherbone).
|
2021-03-08 13:45:09 +01:00 |
|
fk33.py
|
targets/xilinx: add comment on sys_clk to pll.clkin false path.
|
2021-01-07 08:01:54 +01:00 |
|
fomu.py
|
targets/fomu: modification to ValentyUSB no longer required.
|
2020-11-27 19:40:45 +01:00 |
|
fpc_iii.py
|
Be friendlier about incompatible options.
|
2021-01-29 18:08:38 -07:00 |
|
genesys2.py
|
Be friendlier about incompatible options.
|
2021-01-29 18:08:38 -07:00 |
|
hadbadge.py
|
targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
|
2021-01-04 11:38:07 +01:00 |
|
icebreaker.py
|
targets/video: Simplify/Cleanup integration.
|
2021-03-05 14:40:27 +01:00 |
|
kc705.py
|
targets/xilinx: add comment on sys_clk to pll.clkin false path.
|
2021-01-07 08:01:54 +01:00 |
|
kcu105.py
|
targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).
|
2021-03-04 19:49:03 +01:00 |
|
kx2.py
|
targets/xilinx: add comment on sys_clk to pll.clkin false path.
|
2021-01-07 08:01:54 +01:00 |
|
linsn_rv901t.py
|
targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
|
2021-01-04 11:38:07 +01:00 |
|
litefury.py
|
targets/xilinx: add comment on sys_clk to pll.clkin false path.
|
2021-01-07 08:01:54 +01:00 |
|
logicbone.py
|
target/usb_acm: switch git clone to litex-hub/valentyusb repo (up to date with LiteX).
|
2020-11-27 18:53:45 +01:00 |
|
mercury_xu5.py
|
targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).
|
2021-03-04 19:49:03 +01:00 |
|
mimas_a7.py
|
targets/xilinx: add comment on sys_clk to pll.clkin false path.
|
2021-01-07 08:01:54 +01:00 |
|
minispartan6.py
|
targets/xilinx: add comment on sys_clk to pll.clkin false path.
|
2021-01-07 08:01:54 +01:00 |
|
mist.py
|
platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support.
|
2021-03-03 18:05:24 +01:00 |
|
nereid.py
|
targets/xilinx: add comment on sys_clk to pll.clkin false path.
|
2021-01-07 08:01:54 +01:00 |
|
netv2.py
|
Be friendlier about incompatible options.
|
2021-01-29 18:08:38 -07:00 |
|
nexys4ddr.py
|
targets/video: Simplify/Cleanup integration.
|
2021-03-05 14:40:27 +01:00 |
|
nexys_video.py
|
targets/video: Simplify/Cleanup integration.
|
2021-03-05 14:40:27 +01:00 |
|
orangecrab.py
|
orangecrab: remove dm_remapping workaround: we are now using Wihsbone/L2 path with VexRiscv-SMP on this board.
|
2021-01-25 11:52:59 +01:00 |
|
pano_logic_g2.py
|
Be friendlier about incompatible options.
|
2021-01-29 18:08:38 -07:00 |
|
pipistrello.py
|
targets: add --sys-clk-freq support to all targets.
|
2020-11-12 18:07:28 +01:00 |
|
qmtech_ep4ce15.py
|
targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
|
2021-01-04 11:38:07 +01:00 |
|
qmtech_wukong.py
|
Be friendlier about incompatible options.
|
2021-01-29 18:08:38 -07:00 |
|
redpitaya.py
|
targets/xilinx: add comment on sys_clk to pll.clkin false path.
|
2021-01-07 08:01:54 +01:00 |
|
sds1104xe.py
|
targets/sds1104xe: Enable both Ethernet/Etherbone with hybrid LiteEthMAC.
|
2021-02-23 15:27:50 +01:00 |
|
simple.py
|
targets/simple: add try/except on leds.
|
2020-11-12 14:26:00 +01:00 |
|
tagus.py
|
targets/xilinx: add comment on sys_clk to pll.clkin false path.
|
2021-01-07 08:01:54 +01:00 |
|
tec0117.py
|
tec0117: get SDRAM working and increase sys_clk_freq to 25MHz.
|
2021-02-01 13:32:01 +01:00 |
|
tinyfpga_bx.py
|
targets: add --sys-clk-freq support to all targets.
|
2020-11-12 18:07:28 +01:00 |
|
trellisboard.py
|
Be friendlier about incompatible options.
|
2021-01-29 18:08:38 -07:00 |
|
ulx3s.py
|
Be friendlier about incompatible options.
|
2021-01-29 18:08:38 -07:00 |
|
vc707.py
|
targets/xilinx: add comment on sys_clk to pll.clkin false path.
|
2021-01-07 08:01:54 +01:00 |
|
vcu118.py
|
targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).
|
2021-03-04 19:49:03 +01:00 |
|
versa_ecp5.py
|
targets/versa_ecp5: Fix LiteEthPHYRMGII tx/rx delays (need to be updated due to a bug fix in the ECP5RGMII PHY).
|
2021-03-08 17:39:13 +01:00 |
|
xcu1525.py
|
targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).
|
2021-03-04 19:49:03 +01:00 |
|
zcu104.py
|
targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).
|
2021-03-04 19:49:03 +01:00 |
|
ztex213.py
|
Support file for the ZTEX USB-FPGA Module 2.13
|
2021-01-30 05:19:18 -05:00 |
|
zybo_z7.py
|
targets/xilinx: add comment on sys_clk to pll.clkin false path.
|
2021-01-07 08:01:54 +01:00 |
61f44739d7