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__init__.py
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Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
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2020-02-03 09:36:30 +01:00 |
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ac701.py
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targets/ac701: rename --ethernet-phy to --eth-phy for consistency with others targets.
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2021-01-08 18:50:01 +01:00 |
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acorn_cle_215.py
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Be friendlier about incompatible options.
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2021-01-29 18:08:38 -07:00 |
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aller.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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alveo_u250.py
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targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).
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2021-03-04 19:49:03 +01:00 |
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arrow_sockit.py
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sockit: Add an option to plug in an UART via the GPIO daughter board
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2021-02-10 14:52:19 +07:00 |
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arty.py
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targets/arty: rebase/merge PR179, rename adaptor to adapter.
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2021-02-25 09:36:26 +01:00 |
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arty_s7.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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c10lprefkit.py
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targets/c10lprefkit: fix default sys-clk-freq.
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2021-01-12 16:15:52 +01:00 |
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camlink_4k.py
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camlink_4k: disable leds when serial is used (since pin is shared).
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2021-01-25 12:19:29 +01:00 |
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colorlight_5a_75x.py
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Be friendlier about incompatible options.
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2021-01-29 18:08:38 -07:00 |
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colorlight_i5.py
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targets/colorlight_i5: use .bit stream instead of .svf when loading.
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2021-02-03 08:17:24 +09:00 |
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crosslink_nx_evn.py
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nexus: Allow selection of toolchain
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2020-11-25 09:45:25 +00:00 |
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crosslink_nx_vip.py
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nexus: Allow selection of toolchain
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2020-11-25 09:45:25 +00:00 |
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de0nano.py
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targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
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2021-01-04 11:38:07 +01:00 |
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de1soc.py
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targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
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2021-01-04 11:38:07 +01:00 |
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de2_115.py
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targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
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2021-01-04 11:38:07 +01:00 |
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de10lite.py
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platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support.
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2021-03-03 18:05:24 +01:00 |
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de10nano.py
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platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support.
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2021-03-03 18:05:24 +01:00 |
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deca.py
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platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support.
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2021-03-03 18:05:24 +01:00 |
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ecp5_evn.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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ecpix5.py
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ecpix5: Add Etherbone (--with-etherbone).
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2021-03-08 13:45:09 +01:00 |
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fk33.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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fomu.py
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targets/fomu: modification to ValentyUSB no longer required.
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2020-11-27 19:40:45 +01:00 |
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fpc_iii.py
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Be friendlier about incompatible options.
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2021-01-29 18:08:38 -07:00 |
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genesys2.py
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Be friendlier about incompatible options.
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2021-01-29 18:08:38 -07:00 |
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hadbadge.py
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targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
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2021-01-04 11:38:07 +01:00 |
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icebreaker.py
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targets/video: Simplify/Cleanup integration.
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2021-03-05 14:40:27 +01:00 |
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kc705.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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kcu105.py
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targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).
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2021-03-04 19:49:03 +01:00 |
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kx2.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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linsn_rv901t.py
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targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
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2021-01-04 11:38:07 +01:00 |
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litefury.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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logicbone.py
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target/usb_acm: switch git clone to litex-hub/valentyusb repo (up to date with LiteX).
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2020-11-27 18:53:45 +01:00 |
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mercury_xu5.py
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targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).
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2021-03-04 19:49:03 +01:00 |
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mimas_a7.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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minispartan6.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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mist.py
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platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support.
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2021-03-03 18:05:24 +01:00 |
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nereid.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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netv2.py
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Be friendlier about incompatible options.
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2021-01-29 18:08:38 -07:00 |
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nexys4ddr.py
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targets/video: Simplify/Cleanup integration.
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2021-03-05 14:40:27 +01:00 |
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nexys_video.py
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targets/video: Simplify/Cleanup integration.
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2021-03-05 14:40:27 +01:00 |
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orangecrab.py
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orangecrab: remove dm_remapping workaround: we are now using Wihsbone/L2 path with VexRiscv-SMP on this board.
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2021-01-25 11:52:59 +01:00 |
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pano_logic_g2.py
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Be friendlier about incompatible options.
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2021-01-29 18:08:38 -07:00 |
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pipistrello.py
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targets: add --sys-clk-freq support to all targets.
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2020-11-12 18:07:28 +01:00 |
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qmtech_ep4ce15.py
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targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
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2021-01-04 11:38:07 +01:00 |
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qmtech_wukong.py
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Be friendlier about incompatible options.
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2021-01-29 18:08:38 -07:00 |
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redpitaya.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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sds1104xe.py
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targets/sds1104xe: Enable both Ethernet/Etherbone with hybrid LiteEthMAC.
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2021-02-23 15:27:50 +01:00 |
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simple.py
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targets/simple: add try/except on leds.
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2020-11-12 14:26:00 +01:00 |
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tagus.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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tec0117.py
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tec0117: get SDRAM working and increase sys_clk_freq to 25MHz.
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2021-02-01 13:32:01 +01:00 |
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tinyfpga_bx.py
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targets: add --sys-clk-freq support to all targets.
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2020-11-12 18:07:28 +01:00 |
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trellisboard.py
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Be friendlier about incompatible options.
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2021-01-29 18:08:38 -07:00 |
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ulx3s.py
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Be friendlier about incompatible options.
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2021-01-29 18:08:38 -07:00 |
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vc707.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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vcu118.py
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targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).
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2021-03-04 19:49:03 +01:00 |
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versa_ecp5.py
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targets/versa_ecp5: Fix LiteEthPHYRMGII tx/rx delays (need to be updated due to a bug fix in the ECP5RGMII PHY).
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2021-03-08 17:39:13 +01:00 |
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xcu1525.py
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targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).
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2021-03-04 19:49:03 +01:00 |
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zcu104.py
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targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).
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2021-03-04 19:49:03 +01:00 |
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ztex213.py
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Support file for the ZTEX USB-FPGA Module 2.13
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2021-01-30 05:19:18 -05:00 |
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zybo_z7.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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