litex/migen/bus/dfi.py

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from migen.fhdl.structure import *
from migen.fhdl.module import Module
from migen.genlib.record import *
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def phase_description(a, ba, d):
return [
("address", a, DIR_M_TO_S),
("bank", ba, DIR_M_TO_S),
("cas_n", 1, DIR_M_TO_S),
("cke", 1, DIR_M_TO_S),
("cs_n", 1, DIR_M_TO_S),
("ras_n", 1, DIR_M_TO_S),
("we_n", 1, DIR_M_TO_S),
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("wrdata", d, DIR_M_TO_S),
("wrdata_en", 1, DIR_M_TO_S),
("wrdata_mask", d//8, DIR_M_TO_S),
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("rddata_en", 1, DIR_M_TO_S),
("rddata", d, DIR_S_TO_M),
("rddata_valid", 1, DIR_S_TO_M)
]
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class Interface(Record):
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def __init__(self, a, ba, d, nphases=1):
layout = [("p"+str(i), phase_description(a, ba, d)) for i in range(nphases)]
Record.__init__(self, layout)
self.phases = [getattr(self, "p"+str(i)) for i in range(nphases)]
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for p in self.phases:
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p.cas_n.reset = 1
p.cs_n.reset = 1
p.ras_n.reset = 1
p.we_n.reset = 1
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# Returns pairs (DFI-mandated signal name, Migen signal object)
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def get_standard_names(self, m2s=True, s2m=True):
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r = []
add_suffix = len(self.phases) > 1
for n, phase in enumerate(self.phases):
for field, size, direction in phase.layout:
if (m2s and direction == DIR_M_TO_S) or (s2m and direction == DIR_S_TO_M):
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if add_suffix:
if direction == DIR_M_TO_S:
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suffix = "_p" + str(n)
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else:
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suffix = "_w" + str(n)
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else:
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suffix = ""
r.append(("dfi_" + field + suffix, getattr(phase, field)))
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return r
class Interconnect(Module):
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def __init__(self, master, slave):
self.comb += master.connect(slave)