2022-01-17 04:17:10 -05:00
|
|
|
[> 2022.04, released on XXX
|
|
|
|
|
----------------------------------------
|
|
|
|
|
|
|
|
|
|
[> Issues resolved
|
|
|
|
|
------------------
|
|
|
|
|
- software/bios/mem_write: Fix write address increment.
|
|
|
|
|
|
|
|
|
|
[> Added Features
|
|
|
|
|
-----------------
|
|
|
|
|
- litex_setup: Add minimal/standard/full install configs.
|
|
|
|
|
- soc/arguments: Improve default/help, add parser groups.
|
|
|
|
|
- LiteSPI/phy: Simplify integration on targets.
|
|
|
|
|
- openocd/stream: Simplify ECP5 JTAG-UART/JTAGBone use.
|
|
|
|
|
- tools/litex_cli: Allow passing reg name to --read/--write.
|
|
|
|
|
- soc/add_spi_sdcard: Allow optional Tristate (useful on ULX3S).
|
|
|
|
|
- software/bios: Add new mem_cmd memory comparison commmand.
|
|
|
|
|
- cpu/rocket: Increase IRQ lines to 8.
|
|
|
|
|
- cpu/serv: Add MDU support.
|
|
|
|
|
- cpu/marocchino: Add initial support.
|
|
|
|
|
- cpu/eos_s3: Add LiteX BIOS/Bare Metal software support.
|
2022-01-19 03:57:10 -05:00
|
|
|
- litex_sim: Add .json support for --rom/ram/sdram-init.
|
2022-01-17 04:17:10 -05:00
|
|
|
|
|
|
|
|
[> API changes/Deprecation
|
|
|
|
|
--------------------------
|
|
|
|
|
- Fully deprecate SoCSDRAM/SPIFlash core (replaced by LiteSPI).
|
|
|
|
|
|
2022-01-05 02:53:10 -05:00
|
|
|
[> 2021.12, released on January 5th 2022
|
|
|
|
|
----------------------------------------
|
2022-01-03 13:29:05 -05:00
|
|
|
|
|
|
|
|
[> Issues resolved
|
|
|
|
|
------------------
|
|
|
|
|
- software/linker: Fix initialized global variables.
|
|
|
|
|
- build/xilinx: Fix Ultrascale SDROutput/Input.
|
|
|
|
|
- cpu/rocket/crt0.s: Fix alignements.
|
|
|
|
|
- core/video: Fix missing ClockDomainsRenamer in specific DRAM's width case.
|
|
|
|
|
- mor1kx: Fix --cpu-type=None --with-ethernet case.
|
|
|
|
|
- build/lattice: Fix LatticeiCE40SDROutputImpl.
|
|
|
|
|
- soc/interconnect/axi: Fix 4KB bursts.
|
|
|
|
|
|
|
|
|
|
[> Added Features
|
|
|
|
|
-----------------
|
|
|
|
|
- integration/builder: Check if full software re-build is required when a CPU is used.
|
|
|
|
|
- cores/clock: Add Gowin PLL support.
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|
|
|
|
- build/gowin: Add initial HyperRam support.
|
|
|
|
|
- build/gowin: Add differential Input/Output support.
|
|
|
|
|
- build/lattice: Add DDRTristate support.
|
|
|
|
|
- cores/gpio: Add external Tristate support.
|
|
|
|
|
- tools/json2dts: Make it more generic (now also used with OpenRisc/Mor1kx).
|
|
|
|
|
- cpu/rocket: Add SMP support (up to quad-core).
|
|
|
|
|
- software/bios/boot: Allow frame reception to time out (for litex_term auto-calibration).
|
|
|
|
|
- tools/litex_term: Add automatic settings calibration and --safe mode.
|
|
|
|
|
- build/quicklogic: Add initial support.
|
|
|
|
|
- cores/icap/7-Series: Add register read capability.
|
|
|
|
|
- cores/video: Add RGB565 support to VideoFrameBuffer.
|
|
|
|
|
- soc: Raise custom SoCError Exception and disable traceback/exception.
|
|
|
|
|
- soc/add_pcie: Automatically set Endpoint's endianness to PHY's endianness.
|
|
|
|
|
- build/efinix: Add initial Trion and Titanium support.
|
|
|
|
|
- fhdl/verilog: Cleanup/Simplify verilog generation.
|
|
|
|
|
- fhdl/memory: Cleanup/Simplify and add support for Efinix case.
|
|
|
|
|
- cpu/ibex: Add interrupt support.
|
|
|
|
|
- tools/litex_client: Add --length parameter for MMAP read accesses.
|
|
|
|
|
- software/bios/cpu: Add CPU tests in CI.
|
|
|
|
|
- litex_sim/xgmii_ethernet: Improve models.
|
|
|
|
|
- litex_setup: Cleanup/Simplify and switch to proper "--" commands (with retro-compat).
|
|
|
|
|
- cores/jtag: Add ECP5 support.
|
|
|
|
|
- cores/led: Add WS2812/NeoPixel core.
|
|
|
|
|
- cpu/femtorv: Finish integration and add variants support.
|
|
|
|
|
- cpu/eos-s3: Add initial support.
|
|
|
|
|
- build/anlogic: Add initial support.
|
|
|
|
|
- cpu/microwatt: Add Xilinx multiplier support.
|
|
|
|
|
- cpu/vexriscv/cfu: Improve integration.
|
|
|
|
|
- soc/interconnect: Add initial AHB support (AHB2Wishbone).
|
|
|
|
|
- cpu/gowin_emcu: Add initial Gowin EMCU support.
|
|
|
|
|
- cpu/zynq7000: Add initial BIOS/software support.
|
|
|
|
|
- cpu/zynq7000: Add TCL support.
|
|
|
|
|
- core/prbs: Add error behaviour configuration on saturation.
|
|
|
|
|
- software/bios: Add write size option to mem_write cmd.
|
|
|
|
|
- LitePCIe/phy: Cleanup 7-Series PHY integration.
|
|
|
|
|
- LitePCIe/dma Add LitePCIeDMAStatus module.
|
|
|
|
|
- LitePCIe/software: Improve kernel/user-space utilities.
|
|
|
|
|
- LiteDRAM/litedram_gen: Improve ECP5 support.
|
|
|
|
|
- LiteDRAM/phy: Add initial LPDDR5 support.
|
|
|
|
|
- LiteDRAM/frontend: Refactor DRAM FIFO and add optional bypass mode.
|
|
|
|
|
- LiteEth/core: Add 32-bit/64-bit datapath support.
|
|
|
|
|
- LiteEth/phy: Add 10Gbps / Xilinx XGMII support.
|
|
|
|
|
- LiteEth/phy: Add 1Gbps / Efinix RGMII support.
|
|
|
|
|
- LiteSPI/phy: Simplify SDR/DDR PHYs.
|
|
|
|
|
- LiteHyperBus: Add 16-bit support.
|
|
|
|
|
|
|
|
|
|
[> API changes/Deprecation
|
|
|
|
|
--------------------------
|
|
|
|
|
- software: Replace libbase with picolibc (new requirements: meson/ninja).
|
|
|
|
|
- amaranth: Switch from nMigen to Amaranth HDL.
|
|
|
|
|
|
2021-09-15 09:05:47 -04:00
|
|
|
[> 2021.08, released on September 15th 2021
|
|
|
|
|
-------------------------------------------
|
2021-05-17 03:58:46 -04:00
|
|
|
|
|
|
|
|
[> Issues resolved
|
|
|
|
|
------------------
|
2021-06-02 04:46:53 -04:00
|
|
|
- wishbone/UpConverter: Fix SEL propagation.
|
2021-09-15 06:08:30 -04:00
|
|
|
- cores/i2s: Fix SYNC sampling.
|
|
|
|
|
- BIOS/lib*: Fix GCC warnings.
|
|
|
|
|
- cpu/software: Fix stack alignment issues.
|
|
|
|
|
- cpu/blackparrot: Fix integration.
|
|
|
|
|
- interconnect/axi: Fix valid signal in connect_to_pads for axi lite.
|
|
|
|
|
- software/hw/common: Fix _csr_rd_buf/_csr_wr_buf for sizeof(buf[0]) < CSR_DW_BYTES case.
|
|
|
|
|
- software/soc.h: Fix interoperability with assembly.
|
|
|
|
|
- interconnect/stream: Fix n=1 case on Multiplexer/Demultiplexer.
|
|
|
|
|
- interconnect/axi: Fix BURST_WRAP case on AXIBurst2Beat.
|
|
|
|
|
- cpu/VexRiscv-SMP: Fix build without a memory bus.
|
|
|
|
|
- cpu/software: Fix CLANG detection.
|
|
|
|
|
- build/software: Force a fresh software build when cpu-type/variant is changed.
|
|
|
|
|
- cores/uart: Fix TX reset level.
|
|
|
|
|
- BIOS: Fix PHDR link error.
|
|
|
|
|
- BIOS: Fix build-id link error.
|
|
|
|
|
- LiteDRAM: Fix Artix7/DDR3 calibraiton at low speed.
|
2021-05-17 03:58:46 -04:00
|
|
|
|
|
|
|
|
[> Added Features
|
|
|
|
|
-----------------
|
2021-09-15 06:08:30 -04:00
|
|
|
- cores/video: Add 7-Series HDMI PHY over GTPs.
|
|
|
|
|
- cores/jtagbone: Allow JTAG chain selection.
|
|
|
|
|
- programmer: Add iCESugar programmer.
|
|
|
|
|
- cpu/vexriscv: Add CFU support.
|
|
|
|
|
- soc/controller: Add separate SoC/CPU reset fields.
|
|
|
|
|
- BIOS/liblitedram: Add debug capabilities, minor improvements.
|
|
|
|
|
- cpu/femtoRV: Add initial FemtoRV support.
|
|
|
|
|
- cores/uart: Cleaned-up, Add optional TX-Flush.
|
|
|
|
|
- cores/usb_ohci: Add initial SpinalHDL's USB OHCI support (integrated in Linux-on-LiteX-Vexriscv).
|
|
|
|
|
- stream: Add Gate Module.
|
|
|
|
|
- soc/builder: Allow linking external software packages.
|
|
|
|
|
- soc/software: Allow registering init functions.
|
|
|
|
|
- cores/ram: Add init support to Nexus LRAM.
|
|
|
|
|
- cores/spi: Add Manual CS Mode for bulk transfers.
|
|
|
|
|
- cores/VexRiscv-SMP: Make [ID]TLB size configurable.
|
|
|
|
|
- dts: Add GPIO IRQ support.
|
|
|
|
|
- programmer/DFUProg: Allow to specify alt interace and to not reboot.
|
|
|
|
|
- cores/clock/ecp5: Add dynamic phase adjustment signals.
|
|
|
|
|
- tools/litex_sim: Mode SDRAM settings to LiteDRAM's DFI model.
|
|
|
|
|
- build/gowin: Add AsyncResetSynchronizer/DDRInput/DDROutput implementations.
|
|
|
|
|
- build/gowin: Add On-Chip-Oscillator support.
|
|
|
|
|
- build/gowin: Add initial timing constraints support.
|
|
|
|
|
- build/attr_translate: Simplify/Cleanup.
|
|
|
|
|
- programmer/OpenFPGALoader: Add cable and freq options.
|
|
|
|
|
- interconnect/packet: Improve PacketFIFO to handle payload/param separately.
|
|
|
|
|
- clock/ecp5: Add 4-output support.
|
|
|
|
|
- LiteSPI: Simplified/Cleaned-up, new MMAP architecture, applied to LiteX-Boards.
|
|
|
|
|
- soc: Add LiteSPI integration code.
|
|
|
|
|
- LitePCIe: DMA/Controller Simplified/Cleaned-up.
|
|
|
|
|
- soc/add_cpu: Add memory mapping overrides to build log and make an exception for the CPUNone case.
|
|
|
|
|
- programmer: Add ECPprogProgrammer.
|
|
|
|
|
- soc/software: Add Random access option to memtest.
|
|
|
|
|
- tools: Add Renode generator script.
|
|
|
|
|
- tools: Add Zephyr DTS generator script.
|
|
|
|
|
- build/io: Add DDRTristate.
|
|
|
|
|
- cpu/VexRiscv: Restructure config flags for dcache/icache presence.
|
|
|
|
|
- litex_sim: Improve RAM/SDRAM integration and make it closer to LiteX-Boards targets.
|
|
|
|
|
- build/sim: Add ODDR/IDDR/DDRSTristate simulation models.
|
|
|
|
|
- litex_sim: Add SPIFlash support.
|
|
|
|
|
- LiteSPI: Add DDR support and integration in LiteX (rate=1:1, 1:2).
|
|
|
|
|
- build/Vivado: Make pre_synthesis/placement/routing commands similar to platform_commands.
|
|
|
|
|
- LiteDRAM: Refactor C code generator.
|
|
|
|
|
- LiteDRAM: Improve LPDDR4 support.
|
|
|
|
|
- LiteDRAM: Reduce ECC granularity.
|
2021-05-17 03:58:46 -04:00
|
|
|
|
|
|
|
|
[> API changes/Deprecation
|
|
|
|
|
--------------------------
|
|
|
|
|
- soc_core: --integrated-rom-file argument renamed to --integrated-rom-init.
|
|
|
|
|
|
|
|
|
|
|
2021-05-03 05:59:42 -04:00
|
|
|
[> 2021.04, released on May 3th 2021
|
|
|
|
|
------------------------------------
|
|
|
|
|
|
|
|
|
|
[> Issues resolved
|
|
|
|
|
------------------
|
|
|
|
|
- litex_term: Fix Windows/OS-X support.
|
|
|
|
|
- soc/USB-ACM: Fix reset clock domain.
|
|
|
|
|
- litex_json2dts: Various fixes/improvements.
|
|
|
|
|
- cores/clock: Fix US(P)IDELAYCTRL reset sequence.
|
|
|
|
|
- cpu/Vexriscv: Fix Lite variant ABI (has multiplier so can use rv32im).
|
|
|
|
|
- BIOS: Fix various compiler warnings.
|
|
|
|
|
- LiteSDCard: Fix various issues, enable multiblock reads/writes and improve performance.
|
|
|
|
|
- CSR: Fix address wrapping within a CSRBank.
|
|
|
|
|
- soc/add_etherbone: Fix UDPIPCore clock domain.
|
|
|
|
|
- stream/Gearbox: Fix some un-supported cases.
|
|
|
|
|
- cpu/VexRiscv-SMP: Fix build on Intel/Altera devices with specific RAM implementation.
|
|
|
|
|
- timer: Fix AutoDoc.
|
|
|
|
|
- Microwatt/Ethernet: Fix build.
|
|
|
|
|
- soc/software: Link with compiler instead of ld.
|
|
|
|
|
|
|
|
|
|
[> Added Features
|
|
|
|
|
-----------------
|
|
|
|
|
- Lattice-NX: Allow up to 320KB RAMs.
|
|
|
|
|
- BIOS: Allow compilation with UART disabled.
|
|
|
|
|
- litex_json2dts: Simplify/Improve and allow VexRiscv/Mor1kx support.
|
|
|
|
|
- BIOS/i2c: Improve cmd_i2c.
|
|
|
|
|
- BIOS/liblitedram: Various improvements for DDR4/LPDDR.
|
|
|
|
|
- cores/Timer: Add initial unit test.
|
|
|
|
|
- cores: Add initial JTAGBone support on Xilinx FPGAs.
|
|
|
|
|
- litex_term: Improve JTAG-UART support.
|
|
|
|
|
- litex_server: Add JTAGBone support.
|
|
|
|
|
- VexRiscv-SMP: Add --without-out-of-order and --with-wishbone-memory capabilities.
|
|
|
|
|
- BIOS: Allow specify TRIPLE with LITEX_ENV_CC_TRIPLE.
|
|
|
|
|
- litex_client: Add simple --read/--write support.
|
|
|
|
|
- OpenFPGALoader: Add flash method.
|
|
|
|
|
- litex_sim: Add GTKWave savefile generator.
|
|
|
|
|
- litex_term: Add nios2-terminal support.
|
|
|
|
|
- cpu/mor1kx: Add initial SMP support.
|
|
|
|
|
- interconnect/axi: Add tkeep support.
|
|
|
|
|
- cores/gpio: Add IRQ support to GPIOIn.
|
|
|
|
|
- cpu: Add initial lowRISC's Ibex support.
|
|
|
|
|
- build/xilinx/Vivado: Allow tcl script to be added as ip.
|
|
|
|
|
- cores/uart: Rewrite PHYs to reduce resource usage and improve readability.
|
|
|
|
|
- cores/pwm: Add configurable default enable/width/period values.
|
|
|
|
|
- cores/leds: Add optional dimming (through PWM).
|
|
|
|
|
- soc/add_pcie: Allow disabling MSI when not required.
|
|
|
|
|
- export/svd: Add constants to SVD export.
|
|
|
|
|
- BIOS: Allow dynamic Ethernet IP address.
|
|
|
|
|
- BIOS: Add boot command to boot from memory.
|
|
|
|
|
- cores: Add simple VideoOut core with Terminal, ColorBards, Framebuffer + various PHYs (VGA, DVI, HDMI, etc...).
|
|
|
|
|
- csr/EventSourceProcess: Add rising edge support and edge selection.
|
|
|
|
|
- soc/integration: Cleanup/Simplify soc_core/builder.
|
|
|
|
|
- soc/integrated_rom: Add automatic BIOS ROM resize to minimize blockram usage and improve flexibility.
|
|
|
|
|
- interconnect/axi: Add AXILite Clock Domain Crossing.
|
|
|
|
|
- cores/xadc: Add Ultrascale support.
|
|
|
|
|
- soc/add_ethernet: Allow nrxslots/ntxslots configuration.
|
|
|
|
|
- cpu/VexRiscv-SMP: Integrate FPU/RVC support.
|
|
|
|
|
- soc/add_csr: Add auto-allocation mode and switch to it in LiteX's code base.
|
|
|
|
|
- soc/BIOS: Add method to check BIOS requirements during the build and improve error message when not satisfied.
|
|
|
|
|
- LiteEth: Add initial timestamping support.
|
|
|
|
|
- litex_client: Add optional filter to --regs.
|
|
|
|
|
- LiteDRAM: Add LPDDR4 support.
|
|
|
|
|
- BIOS/netboot: Allow specifying .json file.
|
|
|
|
|
- cores/clock: Add initial Gowin GW1N PLL support.
|
|
|
|
|
- LiteSDCard: Add IRQ support.
|
|
|
|
|
|
|
|
|
|
[> API changes/Deprecation
|
|
|
|
|
--------------------------
|
|
|
|
|
- platforms/targets: Move all platforms/targets to https://github.com/litex-hub/litex-boards.
|
|
|
|
|
- litex_term: Remove flashing capability.
|
|
|
|
|
- cores/uart: Disable dynamic baudrate by default (Unused and save resources).
|
|
|
|
|
|
2020-12-30 10:49:15 -05:00
|
|
|
[> 2020.12, released on December 30th 2020
|
|
|
|
|
------------------------------------------
|
2020-10-01 05:46:43 -04:00
|
|
|
|
|
|
|
|
[> Issues resolved
|
|
|
|
|
------------------
|
|
|
|
|
- fix SDCard writes.
|
|
|
|
|
- fix crt0 .data initialize on SERV/Minerva.
|
2020-12-30 03:06:36 -05:00
|
|
|
- fix Zynq7000 AXI HP Slave integration.
|
2020-10-01 05:46:43 -04:00
|
|
|
|
|
|
|
|
[> Added Features
|
|
|
|
|
------------------
|
2020-12-30 03:06:36 -05:00
|
|
|
- Wishbone2CSR: Add registered version and use it on system with SDRAM.
|
|
|
|
|
- litex_json2dts: Add Mor1kx DTS generation support.
|
|
|
|
|
- Build: Add initial Radiant support for NX FPGA family.
|
|
|
|
|
- SoC: Allow ROM to be optionally writable (for contents overwrite over UARTBone/Etherbone).
|
|
|
|
|
- LiteSDCard: Improve BIOS support.
|
|
|
|
|
- UARTBone: Add clock domain support.
|
|
|
|
|
- Clocking: Uniformize reset on iCE40PLL/ECP5PLL.
|
|
|
|
|
- LiteDRAM: Improve calibration and add BIOS debug commands.
|
|
|
|
|
- Clocking: Add initial Ultrascale+ support.
|
2020-10-01 05:46:43 -04:00
|
|
|
- Sim: Allow dynamic enable/disable of tracing.
|
2020-12-30 03:06:36 -05:00
|
|
|
- BIOS: Improve memtest and report.
|
|
|
|
|
- BIOS: Rename/reorganize commands.
|
|
|
|
|
- litex_server: Simplify usage with PCIe and add debug parameter.
|
|
|
|
|
- LitePCIe: Add Ultrascale(+) support up to Gen3 X16.
|
|
|
|
|
- LiteSATA: Add BIOS/Boot integration.
|
2020-10-30 10:41:36 -04:00
|
|
|
- Add litex_cli to provides common RemoteClient functions: get identifier, dump regs, etc...
|
2020-12-30 03:06:36 -05:00
|
|
|
- LiteDRAM: Simplify BIST integration.
|
|
|
|
|
- Toolchains/Programmers: Improve checks/error reporting.
|
|
|
|
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- BIOS: add leds command.
|
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|
|
|
- SoC: Do a full reset of the SoC on reboot (not only the CPU).
|
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|
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- Etherbone: Improve efficiency/performance.
|
|
|
|
|
- LiteDRAM: Improve DDR4/DDR3 calibration.
|
|
|
|
|
- Build: Add initial Oxide support for NX FPGA family.
|
|
|
|
|
- Clock/RAM: Reorganize for better modularity.
|
|
|
|
|
- SPI-OPI: Various improvements for Betrusted.
|
|
|
|
|
- litex_json2dts: Improvements to use it with mor1kx and VexRiscv-SMP.
|
2020-12-30 10:49:15 -05:00
|
|
|
- Microwatt: Add IRQ support.
|
2020-12-30 03:06:36 -05:00
|
|
|
- BIOS: Add i2c_scan command.
|
|
|
|
|
- Builder: Simplify Documentation generation with --doc args on targets.
|
|
|
|
|
- CSR: Add documentation to EventManager registers.
|
|
|
|
|
- BIOS: Allow disabling timestamp for reproducible builds.
|
|
|
|
|
- Symbiflow: Remove workarounds on targets.
|
|
|
|
|
- litex_server: Simplify use on PCIe, allow direct CommXY use in scripts to bypass litex_server.
|
|
|
|
|
- Zynq7000: Improve PS7 configuration support (now supporting .xci/preset/dict)
|
|
|
|
|
- CV32E40P: Improve OBI efficiency.
|
|
|
|
|
- litex_term: Improve upload speed with CRC check enabled, deprecate --no-crc (no longer useful).
|
|
|
|
|
- BIOS: Add mem_list command to list available memory and use mem_xy commands on them.
|
|
|
|
|
- litex_term: Add Crossover and JTAG_UART support.
|
|
|
|
|
- Software: Add minimal bare metal demo app.
|
|
|
|
|
- UART: Add Crossover+Bridge support.
|
|
|
|
|
- VexRiscv-SMP: Integrate AES support.
|
|
|
|
|
- LitePCIe: Allow AXI mastering from FPGA (AXI-Lite and Full).
|
|
|
|
|
- mor1kx: Add standard+fpu and linux+fpu variants.
|
2020-10-01 05:46:43 -04:00
|
|
|
|
|
|
|
|
[> API changes/Deprecation
|
|
|
|
|
--------------------------
|
|
|
|
|
- BIOS: commands have been renamed/reorganized.
|
|
|
|
|
- LiteDRAM: rdcmdphase/wrcmdphase no longer exposed.
|
2020-10-07 10:35:08 -04:00
|
|
|
- CSR: change default csr_data_width from 8 to 32.
|
2020-10-01 05:46:43 -04:00
|
|
|
|
2020-12-30 10:49:15 -05:00
|
|
|
[> 2020.08, released on August 7th 2020
|
|
|
|
|
---------------------------------------
|
2020-05-01 13:07:43 -04:00
|
|
|
|
|
|
|
|
[> Issues resolved
|
|
|
|
|
------------------
|
2020-05-04 03:59:01 -04:00
|
|
|
- Fix flush_cpu_icache on VexRiscv.
|
2020-06-23 06:49:36 -04:00
|
|
|
- Fix `.data` section placed in rom (#566)
|
2020-05-01 13:07:43 -04:00
|
|
|
|
|
|
|
|
[> Added Features
|
|
|
|
|
------------------
|
2020-06-02 09:05:46 -04:00
|
|
|
- Properly integrate Minerva CPU.
|
|
|
|
|
- Add nMigen dependency.
|
|
|
|
|
- Pluggable CPUs.
|
|
|
|
|
- BIOS history, autocomplete.
|
|
|
|
|
- Improve boards's programmers.
|
|
|
|
|
- Add Microwatt CPU support (with GHDL-Yosys-plugin support for FOSS toolchains).
|
|
|
|
|
- Speedup Memtest using an LFSR.
|
|
|
|
|
- Add LedChaser on boards.
|
2020-05-14 03:34:37 -04:00
|
|
|
- Improve WishboneBridge.
|
|
|
|
|
- Improve Diamond constraints.
|
2020-06-02 09:05:46 -04:00
|
|
|
- Use InterconnectPointToPoint when 1 master,1 slave and no address translation.
|
|
|
|
|
- Add CV32E40P CPU support (ex RI5CY).
|
|
|
|
|
- JTAG UART with uart_name=jtag_uart (validated on Spartan6, 7-Series, Ultrascale(+)).
|
|
|
|
|
- Add Symbiflow experimental support on Arty.
|
2020-07-22 17:10:26 -04:00
|
|
|
- Add SDCard (SPI and SD modes) boot from FAT/exFAT filesystems with FatFs.
|
2020-06-11 13:24:54 -04:00
|
|
|
- Simplify boot with boot.json configuration file.
|
2020-06-23 06:49:36 -04:00
|
|
|
- Revert to a single crt0 (avoid ctr/xip variants).
|
2020-07-22 17:10:26 -04:00
|
|
|
- Add otional DMA bus for Cache Coherency on CPU(s) with DMA/Cache Coherency interface.
|
|
|
|
|
- Add AXI-Lite bus standard support.
|
2020-07-28 12:37:23 -04:00
|
|
|
- Add VexRiscv SMP CPU support.
|
2020-05-01 13:07:43 -04:00
|
|
|
|
|
|
|
|
[> API changes/Deprecation
|
|
|
|
|
--------------------------
|
2020-05-14 03:34:37 -04:00
|
|
|
- Add --build --load arguments to targets.
|
2020-05-27 12:45:07 -04:00
|
|
|
- Deprecate soc.interconnect.wishbone.UpConverter (will be rewritten if useful).
|
|
|
|
|
- Deprecate soc.interconnect.wishbone.CSRBank (Does not seem to be used by anyone).
|
|
|
|
|
- Move soc.interconnect.wishbone2csr.WB2CSR to soc.interconnect.wishbone.Wishbone2CSR.
|
|
|
|
|
- Move soc.interconnect.wishbonebridge.WishboneStreamingBridge to soc.cores.uart.Stream2Wishbone.
|
2020-06-02 09:05:46 -04:00
|
|
|
- Rename --gateware-toolchain target parameter to --toolchain.
|
2020-07-23 12:02:58 -04:00
|
|
|
- Integrate Zynq's PS7 as a regular CPU (zynq7000) and deprecate SoCZynq.
|
2020-05-01 13:07:43 -04:00
|
|
|
|
2020-12-30 10:49:15 -05:00
|
|
|
[> 2020.04, released on April 28th, 2020
|
|
|
|
|
----------------------------------------
|
2020-04-28 05:36:44 -04:00
|
|
|
|
|
|
|
|
[> Description
|
|
|
|
|
--------------
|
|
|
|
|
First release of LiteX and the ecosystem of cores!
|
|
|
|
|
|
|
|
|
|
LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create
|
|
|
|
|
Cores/SoCs (with or without CPU).
|
|
|
|
|
|
|
|
|
|
The common components of a SoC are provided directly:
|
|
|
|
|
- Buses and Streams (Wishbone, AXI, Avalon-ST)
|
|
|
|
|
- Interconnect
|
|
|
|
|
- Common cores (RAM, ROM, Timer, UART, etc...)
|
|
|
|
|
- CPU wrappers/integration
|
|
|
|
|
- etc...
|
|
|
|
|
And SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM,
|
|
|
|
|
PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX.
|
|
|
|
|
|
|
|
|
|
It also provides build backends for open-source and vendors toolchains.
|
|
|
|
|
|
|
|
|
|
[> Issues resolved
|
|
|
|
|
------------------
|
|
|
|
|
- NA
|
|
|
|
|
|
|
|
|
|
[> Added Features
|
|
|
|
|
------------------
|
|
|
|
|
- NA
|
|
|
|
|
|
|
|
|
|
[> API changes/Deprecation
|
|
|
|
|
--------------------------
|
|
|
|
|
- https://github.com/enjoy-digital/litex/pull/399: Converting LiteX to use Python modules.
|
