litex/lib/sata/link/__init__.py

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from lib.sata.common import *
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from lib.sata.link.crc import SATACRCInserter, SATACRCChecker
from lib.sata.link.scrambler import SATAScrambler
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from lib.sata.link.cont import SATACONTInserter, SATACONTRemover
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from_rx = [
("idle", 1),
("insert", 32),
("det", 32)
]
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class SATALinkTX(Module):
def __init__(self, phy):
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self.sink = Sink(link_description(32))
self.from_rx = Sink(from_rx)
###
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self.fsm = fsm = FSM(reset_state="IDLE")
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# insert CRC
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crc = SATACRCInserter(link_description(32))
self.submodules += crc
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# scramble
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scrambler = SATAScrambler(link_description(32))
self.submodules += scrambler
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# connect CRC / scrambler
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self.comb += [
Record.connect(self.sink, crc.sink),
Record.connect(crc.source, scrambler.sink)
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]
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# inserter CONT and scrambled data between
# CONT and next primitive
self.cont = cont = BufferizeEndpoints(SATACONTInserter(phy_description(32)), "source")
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# datas / primitives mux
insert = Signal(32)
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self.comb += [
If(self.from_rx.insert,
cont.sink.stb.eq(1),
cont.sink.data.eq(self.from_rx.insert),
cont.sink.charisk.eq(0x0001),
).
Elif(insert,
cont.sink.stb.eq(1),
cont.sink.data.eq(insert),
cont.sink.charisk.eq(0x0001),
).Elif(fsm.ongoing("COPY"),
cont.sink.stb.eq(scrambler.source.stb),
cont.sink.data.eq(scrambler.source.d),
scrambler.source.ack.eq(cont.sink.ack),
cont.sink.charisk.eq(0)
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)
]
self.comb += Record.connect(cont.source, phy.sink)
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# FSM
fsm.act("IDLE",
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scrambler.reset.eq(1),
If(self.from_rx.idle,
insert.eq(primitives["SYNC"]),
If(scrambler.source.stb & scrambler.source.sop,
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If(self.from_rx.det == primitives["SYNC"],
NextState("RDY")
)
)
)
)
fsm.act("RDY",
insert.eq(primitives["X_RDY"]),
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If(~self.from_rx.idle,
NextState("IDLE")
).Elif(self.from_rx.det == primitives["R_RDY"],
NextState("SOF")
)
)
fsm.act("SOF",
insert.eq(primitives["SOF"]),
If(phy.sink.ack,
NextState("COPY")
)
)
fsm.act("COPY",
If(self.from_rx.det == primitives["HOLD"],
insert.eq(primitives["HOLDA"]),
).Elif(~scrambler.source.stb,
insert.eq(primitives["HOLD"]),
).Elif(scrambler.source.stb & scrambler.source.eop & scrambler.source.ack,
NextState("EOF")
)
)
fsm.act("EOF",
insert.eq(primitives["EOF"]),
If(phy.sink.ack,
NextState("WTRM")
)
)
fsm.act("WTRM",
insert.eq(primitives["WTRM"]),
If(self.from_rx.det == primitives["R_OK"],
NextState("IDLE")
).Elif(self.from_rx.det == primitives["R_ERR"],
NextState("IDLE")
)
)
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class SATALinkRX(Module):
def __init__(self, phy):
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self.source = Source(link_description(32))
self.to_tx = Source(from_rx)
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###
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self.fsm = fsm = FSM(reset_state="IDLE")
# CONT remover
self.cont = cont = BufferizeEndpoints(SATACONTRemover(phy_description(32)), "source")
self.comb += Record.connect(phy.source, cont.sink)
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# datas / primitives detection
insert = Signal(32)
det = Signal(32)
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self.comb += \
If(cont.source.stb & (cont.source.charisk == 0b0001),
det.eq(cont.source.data)
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)
# descrambler
self.scrambler = scrambler = SATAScrambler(link_description(32))
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# check CRC
self.crc = crc = SATACRCChecker(link_description(32))
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sop = Signal()
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eop = Signal()
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self.sync += \
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If(fsm.ongoing("IDLE"),
sop.eq(1),
).Elif(fsm.ongoing("COPY"),
If(scrambler.sink.stb & scrambler.sink.ack,
sop.eq(0)
)
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)
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self.comb += eop.eq(det == primitives["EOF"])
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crc_error = Signal()
self.sync += \
If(crc.source.stb & crc.source.eop & crc.source.ack,
crc_error.eq(crc.source.error)
)
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# small fifo to manage HOLD
self.fifo = SyncFIFO(link_description(32), 32)
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# graph
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self.comb += [
cont.source.ack.eq(1),
Record.connect(scrambler.source, crc.sink),
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Record.connect(crc.source, self.fifo.sink),
Record.connect(self.fifo.source, self.source)
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]
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cont_source_data_d = Signal(32)
self.sync += \
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If(cont.source.stb & (det == 0),
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scrambler.sink.d.eq(cont.source.data)
)
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# FSM
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fsm.act("IDLE",
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scrambler.reset.eq(1),
If(det == primitives["X_RDY"],
NextState("RDY")
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)
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)
fsm.act("RDY",
insert.eq(primitives["R_RDY"]),
If(det == primitives["SOF"],
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NextState("WAIT_FIRST")
)
)
fsm.act("WAIT_FIRST",
insert.eq(primitives["R_IP"]),
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If(cont.source.stb & (det == 0),
NextState("COPY")
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)
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)
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self.comb += [
scrambler.sink.sop.eq(sop),
scrambler.sink.eop.eq(eop)
]
fsm.act("COPY",
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scrambler.sink.stb.eq(cont.source.stb & ((det == 0) | eop)),
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insert.eq(primitives["R_IP"]),
If(det == primitives["HOLD"],
insert.eq(primitives["HOLDA"])
).Elif(det == primitives["EOF"],
NextState("WTRM")
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).Elif(self.fifo.fifo.level > 8,
insert.eq(primitives["HOLD"])
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)
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)
fsm.act("EOF",
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insert.eq(primitives["R_IP"]),
If(det == primitives["WTRM"],
NextState("WTRM")
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)
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)
fsm.act("WTRM",
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insert.eq(primitives["R_IP"]),
If(~crc_error,
NextState("R_OK")
).Else(
NextState("R_ERR")
)
)
fsm.act("R_OK",
insert.eq(primitives["R_OK"]),
If(det == primitives["SYNC"],
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NextState("IDLE")
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)
)
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fsm.act("R_ERR",
insert.eq(primitives["R_ERR"]),
If(det == primitives["SYNC"],
NextState("IDLE")
)
)
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# to TX
self.comb += [
self.to_tx.idle.eq(fsm.ongoing("IDLE")),
self.to_tx.insert.eq(insert),
self.to_tx.det.eq(det)
]
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class SATALink(Module):
def __init__(self, phy):
self.tx = SATALinkTX(phy)
self.rx = SATALinkRX(phy)
self.comb += Record.connect(self.rx.to_tx, self.tx.from_rx)
self.sink, self.source = self.tx.sink, self.rx.source