2015-01-06 10:48:19 -05:00
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import math
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2014-11-03 12:54:41 -05:00
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from migen.fhdl.std import *
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2014-12-18 12:02:35 -05:00
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from migen.genlib.resetsync import *
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from migen.genlib.fsm import *
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2014-11-11 04:19:24 -05:00
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from migen.genlib.record import *
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2015-01-16 17:52:41 -05:00
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from migen.genlib.misc import chooser, optree
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from migen.genlib.cdc import *
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2014-12-03 10:32:55 -05:00
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from migen.flow.actor import *
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2015-01-16 17:52:41 -05:00
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from migen.flow.plumbing import Multiplexer, Demultiplexer
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2015-01-06 11:03:27 -05:00
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from migen.flow.plumbing import Buffer
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2014-12-18 12:02:35 -05:00
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from migen.actorlib.fifo import *
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2015-01-16 17:52:41 -05:00
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from migen.actorlib.structuring import Pipeline, Converter
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2014-11-03 12:54:41 -05:00
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2014-12-14 04:45:26 -05:00
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# PHY / Link Layers
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2015-01-19 11:52:05 -05:00
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frequencies = {
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"SATA3" : 150.0,
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"SATA2" : 75.0,
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"SATA1" : 37.5,
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}
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2014-11-11 04:19:24 -05:00
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primitives = {
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"ALIGN" : 0x7B4A4ABC,
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"CONT" : 0X9999AA7C,
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"SYNC" : 0xB5B5957C,
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"R_RDY" : 0x4A4A957C,
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"R_OK" : 0x3535B57C,
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"R_ERR" : 0x5656B57C,
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"R_IP" : 0X5555B57C,
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"X_RDY" : 0x5757B57C,
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"CONT" : 0x9999AA7C,
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"WTRM" : 0x5858B57C,
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"SOF" : 0x3737B57C,
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"EOF" : 0xD5D5B57C,
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"HOLD" : 0xD5D5AA7C,
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"HOLDA" : 0X9595AA7C
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2014-11-11 04:19:24 -05:00
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}
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2014-12-03 05:12:26 -05:00
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def is_primitive(dword):
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for k, v in primitives.items():
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if dword == v:
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return True
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return False
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def decode_primitive(dword):
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for k, v in primitives.items():
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if dword == v:
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return k
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return ""
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2014-12-14 04:52:56 -05:00
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def phy_description(dw):
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layout = [
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("data", dw),
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("charisk", dw//8),
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2014-11-03 12:54:41 -05:00
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]
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2014-12-02 13:24:46 -05:00
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return EndpointDescription(layout, packetized=False)
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2014-11-04 11:35:46 -05:00
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2014-12-14 04:52:56 -05:00
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def link_description(dw):
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layout = [
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("d", dw),
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("error", 1)
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2014-11-04 11:35:46 -05:00
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]
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2014-12-02 13:24:46 -05:00
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return EndpointDescription(layout, packetized=True)
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2014-12-03 10:32:55 -05:00
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2014-12-14 04:45:26 -05:00
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# Transport Layer
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2015-01-06 10:48:19 -05:00
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fis_max_dwords = 2048
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2014-12-14 04:45:26 -05:00
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fis_types = {
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"REG_H2D": 0x27,
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"REG_D2H": 0x34,
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"DMA_ACTIVATE_D2H": 0x39,
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"PIO_SETUP_D2H": 0x5F,
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"DATA": 0x46
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}
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class FISField():
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def __init__(self, dword, offset, width):
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self.dword = dword
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self.offset = offset
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self.width = width
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fis_reg_h2d_cmd_len = 5
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fis_reg_h2d_layout = {
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"type": FISField(0, 0, 8),
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"pm_port": FISField(0, 8, 4),
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"c": FISField(0, 15, 1),
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"command": FISField(0, 16, 8),
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"features_lsb": FISField(0, 24, 8),
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"lba_lsb": FISField(1, 0, 24),
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"device": FISField(1, 24, 8),
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"lba_msb": FISField(2, 0, 24),
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"features_msb": FISField(2, 24, 8),
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"count": FISField(3, 0, 16),
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"icc": FISField(3, 16, 8),
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"control": FISField(3, 24, 8)
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}
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fis_reg_d2h_cmd_len = 5
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fis_reg_d2h_layout = {
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"type": FISField(0, 0, 8),
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"pm_port": FISField(0, 8, 4),
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"i": FISField(0, 14, 1),
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"status": FISField(0, 16, 8),
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"error": FISField(0, 24, 8),
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"lba_lsb": FISField(1, 0, 24),
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"device": FISField(1, 24, 8),
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"lba_msb": FISField(2, 0, 24),
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"count": FISField(3, 0, 16)
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}
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fis_dma_activate_d2h_cmd_len = 1
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fis_dma_activate_d2h_layout = {
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"type": FISField(0, 0, 8),
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"pm_port": FISField(0, 8, 4)
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}
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2015-01-16 16:49:34 -05:00
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fis_pio_setup_d2h_cmd_len = 5
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fis_pio_setup_d2h_layout = {
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"type": FISField(0, 0, 8),
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"pm_port": FISField(0, 8, 4),
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"d": FISField(0, 13, 1),
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"i": FISField(0, 14, 1),
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"status": FISField(0, 16, 8),
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"error": FISField(0, 24, 8),
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"lba_lsb": FISField(1, 0, 24),
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"lba_msb": FISField(2, 0, 24),
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"count": FISField(3, 0, 16),
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"transfer_count": FISField(4, 0, 16),
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}
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2014-12-14 04:45:26 -05:00
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fis_data_cmd_len = 1
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fis_data_layout = {
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"type": FISField(0, 0, 8)
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}
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2014-12-14 04:52:56 -05:00
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def transport_tx_description(dw):
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layout = [
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("type", 8),
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("pm_port", 4),
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("c", 1),
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("command", 8),
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("features", 16),
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("lba", 48),
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("device", 8),
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("count", 16),
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("icc", 8),
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("control", 8),
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2014-12-12 08:31:00 -05:00
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("data", dw)
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2014-12-11 14:19:14 -05:00
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]
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2014-12-12 08:31:00 -05:00
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return EndpointDescription(layout, packetized=True)
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2014-12-11 14:19:14 -05:00
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2014-12-14 04:52:56 -05:00
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def transport_rx_description(dw):
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layout = [
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("type", 8),
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("pm_port", 4),
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("r", 1),
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("d", 1),
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("i", 1),
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("status", 8),
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("error", 8),
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("lba", 48),
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("device", 8),
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("count", 16),
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2015-01-16 16:49:34 -05:00
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("transfer_count", 16),
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2014-12-25 07:11:22 -05:00
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("data", dw),
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("error", 1)
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2014-12-12 12:16:30 -05:00
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]
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return EndpointDescription(layout, packetized=True)
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2014-12-14 04:57:16 -05:00
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# Command Layer
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2014-12-14 04:45:26 -05:00
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regs = {
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"WRITE_DMA_EXT" : 0x35,
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"READ_DMA_EXT" : 0x25,
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"IDENTIFY_DEVICE" : 0xEC
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}
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2014-12-14 04:52:56 -05:00
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def command_tx_description(dw):
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layout = [
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("write", 1),
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("read", 1),
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2015-01-16 16:49:34 -05:00
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("identify", 1),
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2014-12-15 07:26:53 -05:00
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("sector", 48),
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("count", 16),
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("data", dw)
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]
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return EndpointDescription(layout, packetized=True)
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2014-12-14 04:52:56 -05:00
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def command_rx_description(dw):
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2014-12-12 12:16:30 -05:00
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layout = [
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("write", 1),
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("read", 1),
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2015-01-16 16:49:34 -05:00
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("identify", 1),
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("last", 1),
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2014-12-12 12:16:30 -05:00
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("success", 1),
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("failed", 1),
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2014-12-12 08:31:00 -05:00
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("data", dw)
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2014-12-03 10:32:55 -05:00
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]
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return EndpointDescription(layout, packetized=True)
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2014-12-15 09:31:08 -05:00
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def command_rx_cmd_description(dw):
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layout = [
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("write", 1),
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("read", 1),
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2015-01-16 16:49:34 -05:00
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("identify", 1),
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2015-01-06 10:48:19 -05:00
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("last", 1),
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2014-12-15 09:31:08 -05:00
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("success", 1),
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2015-01-16 16:49:34 -05:00
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("failed", 1)
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2014-12-15 09:31:08 -05:00
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]
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return EndpointDescription(layout, packetized=False)
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def command_rx_data_description(dw):
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layout = [
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("data", dw)
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]
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2014-12-15 13:33:38 -05:00
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return EndpointDescription(layout, packetized=True)
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2015-01-06 10:48:19 -05:00
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# HDD
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logical_sector_size = 512 # constant since all HDDs use this
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def dwords2sectors(n):
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return math.ceil(n*4/logical_sector_size)
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def sectors2dwords(n):
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return n*logical_sector_size//4
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# Generic modules
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2014-12-15 13:33:38 -05:00
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@DecorateModule(InsertReset)
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@DecorateModule(InsertCE)
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class Counter(Module):
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def __init__(self, signal=None, **kwargs):
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if signal is None:
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self.value = Signal(**kwargs)
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else:
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self.value = signal
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self.width = flen(self.value)
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self.sync += self.value.eq(self.value+1)
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2015-01-08 16:59:31 -05:00
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2015-01-14 12:18:42 -05:00
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@DecorateModule(InsertReset)
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@DecorateModule(InsertCE)
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class Timeout(Module):
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def __init__(self, length):
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self.reached = Signal()
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###
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value = Signal(max=length)
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self.sync += value.eq(value+1)
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self.comb += [
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self.reached.eq(value == length)
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]
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2015-01-14 03:19:41 -05:00
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# XXX use ModuleDecorator
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2015-01-08 16:59:31 -05:00
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class BufferizeEndpoints(Module):
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def __init__(self, decorated, *args):
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self.decorated = decorated
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endpoints = get_endpoints(decorated)
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sinks = {}
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sources = {}
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for name, endpoint in endpoints.items():
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if name in args or len(args) == 0:
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if isinstance(endpoint, Sink):
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sinks.update({name : endpoint})
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elif isinstance(endpoint, Source):
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sources.update({name : endpoint})
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# add buffer on sinks
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for name, sink in sinks.items():
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buf = Buffer(sink.description)
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self.submodules += buf
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setattr(self, name, buf.d)
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self.comb += Record.connect(buf.q, sink)
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# add buffer on sources
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for name, source in sources.items():
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buf = Buffer(source.description)
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self.submodules += buf
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self.comb += Record.connect(source, buf.d)
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setattr(self, name, buf.q)
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def __getattr__(self, name):
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return getattr(self.decorated, name)
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def __dir__(self):
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return dir(self.decorated)
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