c857f7845e
soc/cores/hyperbus/HyperRAMPHY: Add specific sampling clk_domain.
2024-08-22 19:53:45 +02:00
c09d57d52d
soc/cores/hyperbus: Minor cleanups.
2024-08-22 17:36:47 +02:00
3213cf8f84
soc/cores/hyperbus: Generate shift signal from HyperRAMPHY.
2024-08-22 17:20:54 +02:00
0edcd2da0e
soc/cores/hyperbus: Cleanup Shift-Register and rename signals.
2024-08-22 17:07:06 +02:00
2dd7e3b9b3
soc/cores/hyperbus: Shorten reg signals and use common done for read/write register accesses.
2024-08-22 16:39:30 +02:00
19f47aa317
soc/cores/hyperbus: Directly drive phy.cs.
2024-08-22 16:31:52 +02:00
120715a3d1
soc/cores/hyperbus: Cleanup parameters.
2024-08-22 16:23:03 +02:00
b9210e7553
soc/cores/hyperbus: Also move ClkGen to HyperRAMPHY.
2024-08-22 16:14:28 +02:00
4f0efc2b25
soc/cores/hyperbus: Add HyperRAMPHY and move related logic to it.
2024-08-22 15:41:18 +02:00
f54ecfa5ff
soc/cores/hyperbus: Avoid setting sr directly in FSM, use sr_load/sr_load_value.
2024-08-22 14:49:55 +02:00
6d0ae25d65
Merge pull request #2046 from enjoy-digital/hyperbus_2x
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HyperRAM: Add 2:1 ratio support in addition of 4:1 ratio.
2024-08-21 19:25:41 +02:00
a88cee70c8
test/test_hyperbus: Update.
2024-08-21 19:22:56 +02:00
37823e34b6
soc/cores/hyperbus: Simplify Clk Generation.
2024-08-21 17:10:36 +02:00
ecd9eee5a4
soc/core/hyperbus: Report Clk Ratio on Status register and use it in software to configure latency.
2024-08-21 15:35:21 +02:00
5587f5954d
test/test_hyperbus: Add 2:1 test.
2024-08-21 15:00:11 +02:00
d22669cf05
soc/cores/hyperbus: Handle 4:1/2:1 specific cases separately, default to 4:1 mode (as before).
2024-08-21 12:07:55 +02:00
f6de6e755e
soc/cores/hyperbus: Add cd_io/sync_io.
2024-08-21 11:50:46 +02:00
43879b0f73
soc/cores/hyperbus: Add clk_ratio support to support x1/x2.
2024-08-21 11:41:13 +02:00
22afa34a64
soc/cores/hyperbus: WiP to make increase similarities between x1/x2 versions.
2024-08-21 11:17:55 +02:00
50f0a1057c
soc/cores/hyperbus: Do some tests with sys_2x, seems working.
2024-08-21 10:57:36 +02:00
0b028d3956
soc/cores/hyperbus: Add comment to allow switching to SDRTristate.
2024-08-20 22:05:38 +02:00
60f83b71fa
soc/cores/hyperbus: Avoid dq_oe condition to generate dq_o (was only useful for sim but now avoided).
2024-08-20 21:54:15 +02:00
298a004f08
Merge pull request #2045 from enjoy-digital/hyperbus_io_regs
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Improve HyperRAM core to allow IO Reg inference.
2024-08-20 19:47:01 +02:00
3a37d3ba98
software/libbase/hyperram: Add missing #ifdef.
2024-08-20 17:11:02 +02:00
eb29b40e07
soc/cores/hyperbus: Simplify CS and make it synchronous to allow IO Reg.
2024-08-20 16:19:15 +02:00
1998c74549
soc/cores/hyperbus: Make DQ/RWDS input sync explicit to allow IO Reg.
2024-08-20 15:44:53 +02:00
8b86b16077
soc/cores/hyperbus: Make Rst synchronous to allow IO Reg (even if low speed).
2024-08-20 15:26:26 +02:00
76cf004913
test/test_hyperbus: Update.
2024-08-20 15:17:36 +02:00
b0026937c1
soc/software/libbase: Move HyperRAM init code to libbase/hyperram.c.
2024-08-20 14:58:51 +02:00
a30651e44e
soc/cores/hyperbus: Avoid waiting for clk_phase in IDLE state to reduce latency.
2024-08-20 14:44:33 +02:00
b7605bc633
Merge pull request #2044 from VOGL-electronic/json2dts_zephyr_omit_disabled_handler
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json2dts_zephyr: omit disable handler
2024-08-20 14:29:35 +02:00
bfe000150c
soc/cores/hyperbus: Rework Clk generation to allow having using an IO Reg.
2024-08-20 14:25:23 +02:00
7b413352c2
soc/cores/hyperbus: Directly specify default sys_clk_freq in __init__.
2024-08-20 12:04:23 +02:00
8f5c2dfbca
soc/cores/hyperbus: Fix build with SDRTristate (to prepare tests with it).
2024-08-20 12:03:40 +02:00
3a53a92bb2
soc/cores/hyperbus: Simplify/Rework Data Shift-Out Register.
2024-08-20 11:38:33 +02:00
9c1958d692
soc/cores/hyperbus: Simplify/Rework Data Shift-In Register.
2024-08-20 11:26:58 +02:00
c1403db407
json2dts_zephyr: omit disable handler
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omit disable handler for the sdcard peripherals,
as they still don't have a driver in zephyr and are not in the board dts.
This way the build in zephyr will not fail.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-08-20 11:23:21 +02:00
db86ec08b8
soc/cores/hyperbus: Better split parameters/signals and use intermediate dq_o/oe/i and rwds_o/oe/i signals.
2024-08-20 11:12:17 +02:00
1f71f3d68b
soc/cores/hyperbus: Cleanup CSn/Clk generation and add comments.
2024-08-20 10:40:24 +02:00
a960dc33bc
soc/cores/hyperbus: Minor cleanup changes.
2024-08-20 10:26:34 +02:00
b95b66b554
soc/cores/hyperbus: Switch to Tristate instead of TSTriple and prepare for SDRTristate (not enabled for now).
2024-08-20 10:10:53 +02:00
afc66fd5cf
cores/picorv32: Fix idbus.sel for reads.
2024-08-19 13:34:50 +02:00
bccd1e9c54
CHANGES.md: Update.
2024-08-19 10:37:13 +02:00
6623a5b691
Merge pull request #2028 from VOGL-electronic/spi_ram_add
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soc: add add_spi_ram function
2024-08-16 19:08:48 +02:00
26e7eef3ce
Merge pull request #2042 from pepijndevos/apicula
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Gowin: add dual use gpio options
2024-08-16 18:58:04 +02:00
039be2a248
add dual use gpio options
2024-08-16 15:56:24 +02:00
cbb1adfa7b
Merge pull request #2036 from Mai-Lapyst/gowin-add-apicula
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Adds apicula toolchain to gowin platform
2024-08-15 08:54:40 +02:00
dc3f2d6421
Add missing license header to apicula.py
2024-08-15 01:54:31 +02:00
623536cd6a
Remove empty build_timing_constraints override in GowinApiculaToolchain
2024-08-15 01:52:22 +02:00
e0968b3574
Adds apicula toolchain to gowin platform
2024-08-12 06:55:11 +02:00
Florent Kermarrec
Fin Maaß
Gwenhael Goavec-Merou
Pepijn de Vos
Gwenhael Goavec-Merou
Mai-Lapyst