Commit Graph

15 Commits

Author SHA1 Message Date
Florent Kermarrec ba30a01830 mila: fixes when used without RLE 2014-10-06 12:30:06 +02:00
Florent Kermarrec 6ffed70b59 uart2wishbone: disconnect rx line from shared pads when bridge is selected
(avoid CPU crash when we communicate with the bridge)
2014-08-03 13:15:56 +02:00
Florent Kermarrec f4e6cebab2 clean up 2014-08-03 11:44:27 +02:00
Florent Kermarrec a0df5baa55 host: add support for various csr_data width (8 & 32 tested, but should work with others) 2014-06-26 13:22:21 +02:00
Florent Kermarrec 0f9bc5ad6e fix bit inversion on CSV/PY exports 2014-06-21 19:06:47 +02:00
Florent Kermarrec 074a12b444 create dump class and specific export functions, add python dictionnary export 2014-06-19 13:24:47 +02:00
Florent Kermarrec a737358919 host: split read/export and add csv export 2014-06-17 11:25:10 +02:00
Florent Kermarrec 8719206a3a uart2wishbone: add default baudrate 2014-06-05 15:13:20 +02:00
Florent Kermarrec 31e142fd88 drivers: clean up / fixes 2014-05-22 18:33:28 +02:00
Florent Kermarrec 0bc1cd6f77 fix uart selection when opening wishbone 2014-05-22 16:11:32 +02:00
Florent Kermarrec 1a07116ab1 change export format and simplify usage 2014-05-20 13:16:24 +02:00
Florent Kermarrec ba0382ad92 move some functions in drivers and export layout in csv 2014-05-20 11:36:10 +02:00
Florent Kermarrec 2312127c1f simplify and clean up 2014-05-20 09:56:35 +02:00
Florent Kermarrec 171224329e drivers: add genericity & prog_range_detector, prog_edge_detector methods 2014-04-21 00:17:23 +02:00
Florent Kermarrec 7a489b3135 refactor code 2014-04-20 23:53:33 +02:00