This patch adds the static files needed for the documentation to the
`package_data` field in `setup.py`.
I ran into failures when generating documentation after installing litex
using pipenv which didn't copy these files which in turn caused the
documentation generation to fail.
This change causes all files in the `static` subfolder of the
litex.soc.doc module to be installed as well.
READ_CHECK_TEST_PATTERN_MAX_ERRORS was being computed incorrectly
which could result in integer underflows when computing core via
(max_errors - errors). This could happen e.g. when using
DFIRateConverter, which modifies DFII_PIX_DATA_BYTES. Now we use
DFII_PIX_DATA_BYTES in the equation so this should not happen.
The Linux LiteETH driver parses registers by name. Provide the expected
names for each register: "mac", "mdio", and "buffer", respectively.
For setting up tx and rx slots, the Linux driver expects three pieces
of information: number of tx and rx slots, and slot size. Update
json2dts_linux to provide the appropriate names and values.
When playing with CPUs and variants, users previously had to do a rm -rf build to ensure
a proper software build. Various developers already lost time on it so it's important
to handle it directly in the Builder which is now the case.
-litex_json2dts_linux (previously litex_json2dts).
-litex_json2dts_zephyr (previously litex_zephyr_dts_generator).
-litex_json2renode (previously litex_renode_generator).
litex_json2dts_zephyr and litex_json2renode are now also directly exposed.
- Fix compilation in sdram.c.
- Fix warnings.
- Move Sequential/Random mode printf to memtest.
- Reduce SPI Flash test size (Testing full SPI Flash makes the boot too long, especially in random mode).
Without this change, when `.data` section size wasn't multiple
of word size, `data_loop` in crt0 was jumping over `_edata` and
continued looping. As it works on words and right now 64 bit CPUs
are biggest ones supported - alignment is now 8 bytes.
Also removed `- 4` from stack address, as it needs to be aligned
to 16 bytes on RISC-V.
The current code only works with a memory bus because otherwise
"generate_cluster_name" doesn't get called.
Cluster_name is only needed in the finalize phase.
Therefore, the name will now be generated just before its usage.
Verifiable with:
litex_sim --cpu-type vexriscv_smp (should be broken before this commit)
RISC-V requires stack to be aligned to 16 bytes.
1d5384e669/riscv-elf.md?plain=1#L183
Right now, in bios/linker.ld, `_fstack` is being set to 8 bytes
before the end of sram region.
```
PROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 8);
```
Removing ` - 8` makes it aligned to 16.
Also there are changes in crt0.S for vexriscv,
vexriscv_smp and cv32e40p.
Code that was setting up stack, was adding 4 to its address
for some reason.
Removing it makes it aligned to 8 bytes, and with change in
bios/linker.ld to 16 bytes.
It also fixes `printf` with long long integers on 32bit
CPUs ([relevant issue](https://github.com/riscv/riscv-gcc/issues/63)).
A regular CPU can provides specific mapping constraints and we are overriding provided mapping
with these constraints.
The case of CPUNone is different and we can do the opposite: Give priority to User's mapping.
For the regular CPU case, the override was done silently, it is now logged during the build.
- Rename optional #define and allow defining them externally.
- Add comments.
- Rename FLASH_CHIP_MX25L12833F_QUAD to SPIFLASH_MODULE_QUAD_CAPABLE.
- Rename FLASH_CHIP_MX25L12833F_QPI to SPIFLASH_MODULE_QPI_CAPABLE.
The instructions used for QUAD/QPI are probably different between chips, we could
imagine providing them through the LiteX integration based on the passed SPI Flash
module.
Andreas Galauner
asadaleem-rs
Jędrzej Boczar
enjoy-digital
Piotr Binkowski
Michal Sieron
Tim Ansell
Gabriel Somlo
Filip Kokosinski
David Sawatzke
Christian Klarhorst
Mateusz Holenko
Dan Callaghan