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7543 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 7b8e8a19f3 Support adding Verilog/VHDL files 2013-02-08 20:25:20 +01:00
Sebastien Bourdeauducq 32dcfc6d02 generic_platform: support name remapping 2013-02-08 18:27:46 +01:00
Sebastien Bourdeauducq 9ecfdeccec platforms/rhino: add PCA9555 I2C expander 2013-02-08 17:44:13 +01:00
Sebastien Bourdeauducq fef9d0fc78 generic_platform: fix typo 2013-02-08 17:43:04 +01:00
Sebastien Bourdeauducq 78f8ec1a53 platforms: add M1 2013-02-08 17:42:35 +01:00
Sebastien Bourdeauducq 25882c6c83 platforms: ROACH (incomplete) 2013-02-07 22:38:33 +01:00
Sebastien Bourdeauducq fb5130fc1f Initial version 2013-02-07 22:07:30 +01:00
Florent Kermarrec 21b6772448 - fix timings.py 2013-01-27 13:59:44 +01:00
Sebastien Bourdeauducq 473fd20f8c fhdl/structure: store clock domain name 2013-01-24 13:49:49 +01:00
Sebastien Bourdeauducq 3201554f76 fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert() 2013-01-23 15:13:06 +01:00
Florent Kermarrec 8975fa2e44 - update README... 2013-01-21 22:40:36 +01:00
Florent Kermarrec d7f932b13c - update README 2013-01-21 22:35:22 +01:00
Florent Kermarrec 2079a24151 - Update README 2013-01-21 22:32:23 +01:00
Florent Kermarrec 35495d8896 - Update README 2013-01-21 22:20:44 +01:00
Sebastien Bourdeauducq a94ee3884f software/include: add float.h 2013-01-12 10:57:43 +01:00
Sebastien Bourdeauducq 83f562a76c software/include: add stdbool.h 2013-01-12 10:51:07 +01:00
Sebastien Bourdeauducq 080dbaa206 software: hide and delete .ts files 2013-01-10 18:01:42 +01:00
Sebastien Bourdeauducq 7adee988f2 software: compile compiler-rt ourselves 2013-01-10 17:59:00 +01:00
Sebastien Bourdeauducq d576893bda software/include/base/stdint.h: add INT32_C 2013-01-10 17:58:17 +01:00
Sebastien Bourdeauducq c5c29199be software: run the assembler ourselves to prevent future time wastage due to breakage of our custom Clang toolchain 2013-01-10 17:20:31 +01:00
Sebastien Bourdeauducq c490917aec software/common.mak: remove -fsigned-char from CFLAGS 2013-01-10 17:14:51 +01:00
Sebastien Bourdeauducq e4144f2c7d software/common.mak: use -target instead of deprecated -ccc-host-triple 2013-01-10 17:13:33 +01:00
Sebastien Bourdeauducq b0503aaf85 software/include/base/stdint.h: more definitions 2013-01-10 17:10:29 +01:00
Sebastien Bourdeauducq 314a6c7743 corelogic: complex arithmetic support 2013-01-05 14:18:36 +01:00
Sebastien Bourdeauducq badba89686 fhdl: support nested statement lists 2013-01-05 14:18:15 +01:00
Florent Kermarrec e6042c122c adapt migScope to Migen changes 2013-01-03 01:46:39 +01:00
Sebastien Bourdeauducq 47f5fc70e4 pytholite: fix bug with constant assignment to register 2012-12-19 16:21:57 +01:00
Sebastien Bourdeauducq 9c65402fda pytholite: prune unused registers 2012-12-19 16:03:05 +01:00
Sebastien Bourdeauducq 51f4f920a2 Do not use super() 2012-12-18 14:55:58 +01:00
Sebastien Bourdeauducq 3fae6c8f03 Do not use super() 2012-12-18 14:54:33 +01:00
Sebastien Bourdeauducq 4d0db2cb05 examples/pytholite: fix imports 2012-12-16 20:26:23 +01:00
Sebastien Bourdeauducq b06fbdedd6 fhdl/tools: bitreverse 2012-12-14 23:56:16 +01:00
Sebastien Bourdeauducq 1f350adf14 actorlib/sim/SimActor: do not drive busy low when generator yields None 2012-12-14 23:56:03 +01:00
Sebastien Bourdeauducq a67f483f0f Token: support idle_wait 2012-12-14 19:16:22 +01:00
Sebastien Bourdeauducq 6f99241585 Move Token to migen.flow.transactions 2012-12-14 15:55:38 +01:00
Sebastien Bourdeauducq c44ff8941c Move Token 2012-12-14 15:54:16 +01:00
Sebastien Bourdeauducq 3986790621 Remove ActorNode 2012-12-12 22:52:55 +01:00
Sebastien Bourdeauducq 28b4d99d31 replace some forgotten is_abstract() 2012-12-12 22:36:45 +01:00
Sebastien Bourdeauducq a7227d7d2b Remove ActorNode 2012-12-12 22:20:48 +01:00
Sebastien Bourdeauducq 8163ed4828 Merge branch 'master' of github.com:milkymist/migen 2012-12-06 20:57:30 +01:00
Sebastien Bourdeauducq 053f8ed82c Fix instantiations 2012-12-06 20:57:00 +01:00
Sebastien Bourdeauducq 483b821342 fhdl/structure: do not create Signal in Instance when parameter is int 2012-12-06 20:56:46 +01:00
Sebastien Bourdeauducq 280a87ea69 elsewhere: do not create interface in default param 2012-12-06 17:34:48 +01:00
Sebastien Bourdeauducq 62187aa23d migen/bank: do not create interface in default param 2012-12-06 17:28:28 +01:00
Sebastien Bourdeauducq c3fdf42825 bus/csr: add SRAM 2012-12-06 17:16:17 +01:00
Sebastien Bourdeauducq 0392dd8ac2 bank/csrgen: interface -> bus 2012-12-06 17:15:47 +01:00
Sebastien Bourdeauducq e89c66bf14 bank/csrgen: interface -> bus 2012-12-06 17:15:34 +01:00
Sebastien Bourdeauducq 273d9d285b bank/description: define reset value of read signal 2012-12-05 16:40:44 +01:00
Sebastien Bourdeauducq 34ce934809 actorlib/sim: drive busy high until generator is finished 2012-12-05 16:40:12 +01:00
Sebastien Bourdeauducq 4bcb39699b bus/wishbone/sram: accept memories < 32 bits 2012-12-01 13:04:22 +01:00