2e3c2611a6
software: put network code in a library
2013-05-01 00:12:13 +02:00
8222ee7f46
framebuffer: use DMA controller from Migen
2013-04-30 18:55:35 +02:00
c8810a016f
actorlib/spi: add DMA read controller
2013-04-30 18:55:01 +02:00
c70c71502e
actorlib/spi/SingleGenerator: use CSR alignment bits
2013-04-30 18:54:47 +02:00
dc0304a87b
bank/description/CSRStorage: support alignment bits
2013-04-30 18:53:40 +02:00
51f1ace061
flow/network/CompositeActor: expose unconnected endpoints
2013-04-30 18:53:02 +02:00
4f13c5b74d
flow/network/DataFlowGraph: add add_pipeline
2013-04-30 15:49:51 +02:00
fb83794ef4
actorlib/spi/Collector: cleanup, new APIs
2013-04-28 18:32:46 +02:00
746e452838
actorlib/dma_asmi: support for writes
2013-04-28 18:06:36 +02:00
43ac5c8471
Remove undriven reset signals
2013-04-25 20:19:49 +02:00
de76faf757
Tell the Xilinx crapware that DCM_CLKGEN does not phase align, as some (but not all) of the ISE tools remark.
2013-04-25 20:18:45 +02:00
4ff1175dcf
Use the Migen asynchronous FIFO
2013-04-25 19:43:26 +02:00
d64b64501a
minimac3: move psync
2013-04-25 18:36:45 +02:00
85e06cc100
xilinx_ise: implement NoRetiming synthesis constraint
2013-04-25 14:57:45 +02:00
e97edd7253
genlib/fifo: disable retiming on Gray counter outputs
2013-04-25 14:57:07 +02:00
156ef43ace
genlib/cdc: add NoRetiming
2013-04-25 14:56:45 +02:00
b862b070d6
fhdl/verilog: recursive Special lowering
2013-04-25 14:56:26 +02:00
67c3119249
genlib/fifo: add asynchronous FIFO
2013-04-25 13:30:37 +02:00
fee228a09f
fhdl/specials/memory: do not write address register for async reads
2013-04-25 13:30:05 +02:00
6c08cd67aa
graycounter: expose binary output
2013-04-25 13:11:15 +02:00
0f9df2d732
genlib: add Gray counter
2013-04-24 19:13:36 +02:00
f599fe4ade
Support for resetless clock domains
2013-04-23 11:54:05 +02:00
bd0ae6592e
Add setup.py
2013-04-19 14:04:59 +02:00
6204bcfa10
README: fix quick intro
2013-04-19 14:00:46 +02:00
117b3b8ec7
adc: double-register asynchronous inputs
2013-04-19 12:32:12 +02:00
0dca526a85
milkymist/adc/__init__.py: CounterADC - simple counter-based ADC
...
This is a revised version of the counter-based ADC.
2013-04-19 12:29:17 +02:00
29eaf068f3
xilinx_ise: do not attempt to source settings file on Windows
2013-04-16 22:55:24 +02:00
31b1960188
xilinx_ise: add --no-source option to disable sourcing of ISE settings file
2013-04-16 22:39:35 +02:00
b018fcedc4
dvisampler/chansync: set synced to 0 when control tokens do not arrive at the same time
2013-04-16 22:21:03 +02:00
1ab89d6a62
tftp.h, tftp.c: add tftp_put
2013-04-16 19:23:12 +02:00
22f39b9d26
tftp.c: use symbolic constant for block size
2013-04-16 19:23:12 +02:00
944dd5932d
tftp.c (format_request): pass opcode as argument
2013-04-16 19:23:12 +02:00
aafb3ef8d7
tftp.c: use uintNN_t instead of "unsigned short", etc.
2013-04-16 19:23:12 +02:00
cdb5519272
tftp.h, tftp.c (tftp_get): make "buffer" void and use unsigned char internally
2013-04-16 19:23:12 +02:00
effa71a811
tftp.c: make "packet_data" unsigned and optimize strcpy+strlen
2013-04-16 19:23:12 +02:00
e0e447f0e0
tftp.c (rx_callback): simplify expressions containing unnecessary casts
2013-04-16 19:23:12 +02:00
36613c7955
tftp.c: use symbolic constants for protocol opcodes
2013-04-16 19:23:12 +02:00
65b807b63f
microudp.c: avoid redundant accesses into multi-level structures
2013-04-16 19:23:11 +02:00
ceb0a99d83
Change license to 2-clause BSD
2013-04-15 23:55:30 +02:00
9405729b95
update README
2013-04-15 16:26:49 +02:00
48c1a902e5
adapt to new CSR API
2013-04-14 18:23:37 +02:00
0d21711c1b
dvisampler/chansync: use Record.raw_bits()
2013-04-14 17:06:29 +02:00
8914969760
dvisampler/clocking: insert DCM_CLKGEN before PLL
2013-04-14 16:53:19 +02:00
f833bc9aa9
software/videomixer: use new csr.h
2013-04-14 16:33:00 +02:00
8e11fcf1d0
bus/csr/SRAM: fix Module conversion errors
2013-04-14 13:55:04 +02:00
ea63389823
fhdl: support len() on all values
2013-04-14 13:50:26 +02:00
7a6e56492c
edid.py: sample SCL only every 64 clock cycles, to avoid bouncing
...
Possibly due to SCL rising fairly slowly (in the 0.5-1 us range),
bouncing has been observed while crossing the "forbidden" region
between Vil(max) and Vih(min).
By lowering the sample rate from once per system clock to once
every 64 clock cycles, we make sure we sample at most once during
the bounce interval and thus never see a false edge. (Although we
may see a rising edge one sample time late, which is perfectly
harmless.)
2013-04-12 22:48:46 +02:00
59d64e92e8
mibuild: define memory card pins of the Milkymist One platorm
...
This patch adds the memory card pins to the M1 platform definition in
mibuild.
I've tentatively named them "mmc". As far as I can tell, "MMC" is not
trademarked ("MultiMediaCard" the new "eMMC" would be), and "MMC" is
commonly used in the industry in a descriptive way to refer to this
sort of interface.
The original Verilog-based M1 calls the interface "mc", but since
several names have changed between milkymist and -ng, I thought I'd
use a more familiar name.
Usage example (clock signal divided by powers of two on the MMC TPs):
https://github.com/wpwrak/ming-ddc-debug/blob/counter-on-mmc/build.py
- Werner
2013-04-12 09:51:57 +02:00
75d33a0c05
fhdl/verilog/_printinit: initialize undriven Special inputs (bug reported by Florent Kermarrec)
2013-04-11 18:55:49 +02:00
72ef4b9683
ioo+pytholite: use new Module API
2013-04-10 23:42:46 +02:00
Sebastien Bourdeauducq
Florent Kermarrec
Werner Almesberger