1a4a6eb445
Copy some software code from the original Milkymist SoC.
...
Libbase should keep its RAM usage to a minimum as it is meant to
be executed before the SDRAM is up and running. (Having lots of
code is OK though as we XIP from the flash)
2012-02-03 12:08:17 +01:00
b5cb1083ab
sram: fix WE signal
2012-02-03 10:38:17 +01:00
8a2646a549
Remove explicit bus names
2012-01-27 22:21:08 +01:00
28f00c3a9a
Add on-chip SRAM
2012-01-27 22:09:03 +01:00
6fde54c5aa
Use meaningful class names
2012-01-21 12:25:22 +01:00
f6aa95a4d0
Use new verilog.convert API
2012-01-20 23:00:11 +01:00
f8d5c27ef8
Wishbone: omit fixed LSBs
2012-01-13 17:28:58 +01:00
570ea8ccf8
convtools -> tools
2012-01-13 17:07:46 +01:00
b60abfaa4a
Convert -> convert
2012-01-05 19:27:45 +01:00
3b640c45bb
Use new syntax
2011-12-18 22:02:05 +01:00
6664af73d1
uart: new design using FHDL and bank (TX only, incomplete)
2011-12-18 00:29:37 +01:00
bb21f7584a
32-device, 8-bit CSR bus
2011-12-17 15:54:42 +01:00
1b3edd07ca
norflash tb: use get_fragment
2011-12-17 15:22:26 +01:00
0e30d67fa3
Multiply system clock
2011-12-17 15:00:18 +01:00
85fbe07b94
clkfx module
2011-12-17 15:00:11 +01:00
411e1af980
Proper reset generation
2011-12-16 22:25:26 +01:00
738b45dcbd
Support the new FHDL syntax
2011-12-16 21:30:22 +01:00
ca68097ef6
Pay a bit more attention to PEP8
2011-12-16 16:02:49 +01:00
b487e99bcf
Initial import
2011-12-13 17:33:12 +01:00
Sebastien Bourdeauducq