sadullah
5e4a436089
Vivado Command Update for Systemverilog
...
Add BlackParrot to LiteX setup file
2020-05-12 03:05:41 -04:00
Florent Kermarrec
c06a127909
cpu/microwatt: add pythondata and fix build with it.
2020-05-04 08:46:25 +02:00
Florent Kermarrec
bd8a410047
cpu/minerva: add pythondata and use it to compile the sources.
2020-05-01 20:12:02 +02:00
Florent Kermarrec
e4a4659d4d
litex_setup: add nmigen dependency (used to generate Minerva CPU).
...
This also requires Yosys, but Yosys is already expected to be installed separately.
2020-05-01 19:10:13 +02:00
Florent Kermarrec
6d0896de1d
cpu/serv: switch to pythondata package instead of local git clone.
2020-04-28 10:34:39 +02:00
Florent Kermarrec
ff61b1f6fa
litex_setup: disable automatic clone of BlackParrot/Microwatt CPUs, reorder LiteX data.
...
The support is not fully finished, so let the user install the pythondata for these CPUs manually with pip.
2020-04-28 09:01:06 +02:00
enjoy-digital
317ea7edd1
Merge branch 'master' into litex-sm2py
2020-04-27 22:24:10 +02:00
Florent Kermarrec
a8bf02167a
litex_setup: raise exception on update if repository has been been initialized.
2020-04-12 19:46:56 +02:00
Tim 'mithro' Ansell
ebcb2a4406
Rename litex-data-XXX-YYY to pythondata-XXX-YYY
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
a39a4ec2ed
Only allow fast-forward pulls.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
119985f353
Use the current directory you are running.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
3ae4f8f2de
Adding missing vexriscv CPU.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
ac3fd794f9
Adding missing comma.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
3964565e15
Fixed quotes in `litex_setup.py`
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
d5a21a7522
Converting litex to use Python modules.
2020-04-11 18:37:06 -07:00
Florent Kermarrec
3f1159fa0b
litex_setup: reorganize a bit, add separators/comments.
2020-04-07 11:05:36 +02:00
Tim 'mithro' Ansell
9e324d9e16
Remove symlinking step.
2020-04-06 17:57:32 -07:00
Tim 'mithro' Ansell
7f0ecddfb2
Use shutil.unpack_archive.
2020-04-06 17:45:55 -07:00
Tim 'mithro' Ansell
a1dd8fc883
Ignore SSL errors on CI.
2020-04-06 17:36:09 -07:00
Tim 'mithro' Ansell
2b2aff1274
Improve the path messages a little.
2020-04-06 17:27:24 -07:00
Tim 'mithro' Ansell
6adabae730
Adding SiFive RISC-V toolchain downloading to litex_setup.py
2020-04-06 16:51:14 -07:00
Tim 'mithro' Ansell
59b7db63b1
Fix alignments.
2020-04-06 16:51:14 -07:00
Tim 'mithro' Ansell
dd59dac571
litex_setup: Use subprocess so failures are noticed.
...
os.system doesn't report if any of the commands fail. This means that if
something goes wrong it happily reports success making it hard to debug
issues.
2020-04-06 11:27:40 -07:00
Piotr Binkowski
ff04869c62
litex_setup: add litespi core
2020-03-30 13:43:45 +02:00
Florent Kermarrec
ab4a5d1dc1
litex_setup: add litejesd204b
2019-10-04 10:00:45 +02:00
Florent Kermarrec
3e30c64842
litex_setup: add litex-boards
2019-08-26 09:28:58 +02:00
atommann
a45dbee54f
changing http to https
2019-08-17 16:02:10 +08:00
Florent Kermarrec
ecf999b8c7
soc/cores: add usb_fifo with FT245 USB FIFO PHY from LiteUSB, deprecate LiteUSB
...
LiteUSB was not up to date was not a real USB PHY but was just providing USB FIFO PHYs.
New true USB cores are now available: Daisho, ValentyUSB, so it's better using
then for true USB support. We only keep the FT245 FIFO PHY in LiteX that can be
useful to interface with USB2/USB3 USB FIFOs.
2019-06-24 10:58:36 +02:00
Florent Kermarrec
228f286747
litex_setup: revert default install behaviour but add --user support
2019-04-23 14:53:00 +02:00
Kees Jongenburger
24bdb6487d
Install development packages in the user directory
...
When in development mode install the packages in the user directory using the
--user flag from pip. This allows to install and run without the need for root
access.
2019-04-23 12:23:09 +02:00
Florent Kermarrec
7e53bff39d
litex_setup: add litesata
2019-04-10 18:04:48 +02:00
Florent Kermarrec
20d6fcac61
add litex_setup script to clone and install Migen, LiteX and LiteX's cores
2018-07-20 10:11:41 +02:00