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20 Commits

Author SHA1 Message Date
Florent Kermarrec 17e5249be0 global: pep8 (replace tabs with spaces) 2015-04-13 20:07:07 +02:00
Sebastien Bourdeauducq e1702c422c introduce conversion output object (prevents file IO in FHDL backends) 2015-04-08 20:28:23 +08:00
Sebastien Bourdeauducq 1d1189506a mibuild: support multiple specifications of include file and sources 2015-04-04 18:58:02 +08:00
Sebastien Bourdeauducq c169f0b189 Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions" 
This reverts commit f03aa76292.
 2015-03-30 19:41:16 +08:00
Florent Kermarrec f03aa76292 migen: create VerilogConvert and EDIFConvert classes and return it with convert functions 2015-03-30 11:37:55 +02:00
Florent Kermarrec ea9c1b8e69 fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code" 
This probably breaks simulation with Icarus Verilog (and others simulators?)
 2015-03-18 14:59:22 +01:00
Florent Kermarrec 9adf3f02f2 fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code 
it's generally better to have identical code between simulations and synthesis, but here tricks inserted for simulation are clearly expected to be simplified by synthesis tools, so it's better not inserting them.
 2015-03-17 00:40:26 +01:00
Sebastien Bourdeauducq 6a979a8023 mibuild: sanitize default clock management 2015-03-14 00:10:08 +01:00
Sebastien Bourdeauducq 702d177c85 mibuild: get rid of Platform factory function, cleanup 2015-03-13 23:25:15 +01:00
Yann Sionneau cea1551ae0 mibuild: support pin names in IO extensions 2015-02-18 08:32:31 -07:00
Sebastien Bourdeauducq d51d33af73 mibuild: make resolve_signals public 2015-02-14 03:05:07 -08:00
Florent Kermarrec beef7425ce mibuild: return verilog namespace with build 2015-02-14 03:02:47 -08:00
Florent Kermarrec dbaeaf7833 remove trailing whitespaces 2014-10-17 17:08:46 +08:00
Florent Kermarrec a0d0742664 mibuild/generic_platform: add recursive parameter to add_source_dir 2014-08-02 21:25:51 +08:00
Fabien Marteau f45897c97f mibuild/generic_platform.py: adding ability to use void pins (none fpga pin) for connectors 
Signed-off-by: Fabien Marteau <fabien.marteau@armadeus.com>
 2014-07-09 10:41:51 +02:00
Sebastien Bourdeauducq bf6ab2b4f6 mibuild/generic_platform: fix default value for connectors 2014-02-17 17:40:15 +01:00
Sebastien Bourdeauducq cb2c9f9f7a mibuild: support for expansion connectors 2014-02-16 23:53:50 +01:00
Sebastien Bourdeauducq 3196462311 add support for Verilog include paths 2013-12-12 23:17:51 +01:00
Sebastien Bourdeauducq de830dc743 mibuild: use keyword arguments directly in build_cmdline 2013-12-01 17:56:07 +01:00
Sebastien Bourdeauducq be3b603b17 merge Mibuild into Migen 2013-11-23 10:45:15 +01:00